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DesignTools.createCeSrRstPinsToVCC() to detect gnd to invert #664

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merged 6 commits into from
May 10, 2023

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@eddieh-xlnx eddieh-xlnx commented May 3, 2023

DesignTools.createCeSrRstPinsToVCC() to now create a SRST[12] site pin connected to the VCC net if the FF cell's sitewire is empty or connected to the GND net.

Also revert the postProcess() method of #636 which wrongly created the environment for triggering the old behaviour for adding this site pin.

Add support for UltraScale parts too.

@eddieh-xlnx eddieh-xlnx force-pushed the fix_srst_inv branch 2 times, most recently from 7ecbd59 to 8765ac5 Compare May 3, 2023 16:53
@eddieh-xlnx eddieh-xlnx merged commit d6a6b5b into master May 10, 2023
@eddieh-xlnx eddieh-xlnx deleted the fix_srst_inv branch May 10, 2023 21:25
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2 participants