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Add DesignTools.getConnectedBELPins() #864

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merged 4 commits into from
Oct 30, 2023
Merged

Add DesignTools.getConnectedBELPins() #864

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747e9d4
Add testGetConnected{Cells,BELPins}()
eddieh-xlnx Oct 30, 2023
2181f32
Add DesignTools.getConnectedBELPins()
eddieh-xlnx Oct 30, 2023
4f3efcb
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eddieh-xlnx Oct 30, 2023
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eddieh-xlnx Oct 30, 2023
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49 changes: 38 additions & 11 deletions src/com/xilinx/rapidwright/design/DesignTools.java
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Original file line number Diff line number Diff line change
Expand Up @@ -50,6 +50,7 @@
import java.util.PriorityQueue;
import java.util.Queue;
import java.util.Set;
import java.util.function.Consumer;
import java.util.stream.Collectors;

import com.xilinx.rapidwright.design.blocks.PBlock;
Expand Down Expand Up @@ -1996,38 +1997,64 @@ public static boolean stampPlacement(Design design, Module stamp, Map<String,Sit
}

/**
* Looks in the site instance for cells connected to this site pin.
* @param pin The pint to examine for connected cells
* @return List of connected cells to this pin
* Looks in the site instance for BEL pins connected to this site pin.
* @param pin The SitePinInst to examine for connected BEL pins
* param action Perform this action on each conncted BELPin
*/
public static Set<Cell> getConnectedCells(SitePinInst pin) {
HashSet<Cell> cells = new HashSet<Cell>();
private static void foreachConnectedBELPin(SitePinInst pin, Consumer<BELPin> action) {
SiteInst si = pin.getSiteInst();
if (si == null) return cells;
if (si == null) {
return;
}
for (BELPin p : pin.getBELPin().getSiteConns()) {
if (p.getBEL().getBELClass() == BELClass.RBEL) {
SitePIP pip = si.getUsedSitePIP(p.getBELName());
if (pip == null) continue;
if (p.isOutput()) {
p = pip.getInputPin().getSiteConns().get(0);
Cell c = si.getCell(p.getBELName());
if (c != null) cells.add(c);
action.accept(p);
} else {
for (BELPin snk : pip.getOutputPin().getSiteConns()) {
Cell c = si.getCell(snk.getBELName());
if (c != null) cells.add(c);
action.accept(snk);
}
}
} else {
Cell c = si.getCell(p.getBELName());
if (c != null && c.getLogicalPinMapping(p.getName()) != null) {
cells.add(c);
action.accept(p);
}
}
}
}

/**
* Looks in the site instance for cells connected to this site pin.
* @param pin The SitePinInst to examine for connected cells
* @return Set of connected cells to this pin
*/
public static Set<Cell> getConnectedCells(SitePinInst pin) {
final HashSet<Cell> cells = new HashSet<>();
SiteInst si = pin.getSiteInst();
foreachConnectedBELPin(pin, (p) -> {
Cell c = si.getCell(p.getBELName());
if (c != null) {
cells.add(c);
}
});
return cells;
}

/**
* Looks in the site instance for BEL pins connected to this site pin.
* @param pin The SitePinInst to examine for connected BEL pins
* @return Set of BEL pins to this site pin
*/
public static Set<BELPin> getConnectedBELPins(SitePinInst pin) {
HashSet<BELPin> pins = new HashSet<>();
foreachConnectedBELPin(pin, pins::add);
return pins;
}

/**
* Quick and dumb placement of a cell. Does not attempt
* any optimization and will not change the placement
Expand Down
60 changes: 60 additions & 0 deletions test/src/com/xilinx/rapidwright/design/TestDesignTools.java
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Original file line number Diff line number Diff line change
Expand Up @@ -1224,4 +1224,64 @@ public void testGetConnectionPIPsBiDir() {
Assertions.assertNotNull(pips);
Assertions.assertEquals(9, pips.size());
}

@Test
public void testGetConnectedCells() {
Design design = RapidWrightDCP.loadDCP("picoblaze_ooc_X10Y235.dcp");
SiteInst si = design.getSiteInstFromSiteName("SLICE_X15Y238");
{
SitePinInst spi = si.getSitePinInst("E3");
Assertions.assertEquals("[processor/data_path_loop[4].arith_logical_lut/LUT6(BEL: E6LUT), processor/data_path_loop[4].arith_logical_lut/LUT5(BEL: E5LUT)]",
DesignTools.getConnectedCells(spi).toString());
}
{
SitePinInst spi = si.getSitePinInst("E6");
Assertions.assertEquals("[processor/data_path_loop[4].arith_logical_lut/LUT6(BEL: E6LUT)]", DesignTools.getConnectedCells(spi).toString());
}
{
SitePinInst spi = si.getSitePinInst("D_I");
Assertions.assertEquals("[output_port_z_reg[4](BEL: DFF2)]", DesignTools.getConnectedCells(spi).toString());
}
{
SitePinInst spi = si.getSitePinInst("CKEN2");
Assertions.assertEquals("[output_port_z_reg[4](BEL: DFF2)]", DesignTools.getConnectedCells(spi).toString());
}
{
DesignTools.createMissingSitePinInsts(design, design.getNet("clk"));
SitePinInst spi = si.getSitePinInst("CLK2");
Assertions.assertEquals("[processor/data_path_loop[7].arith_logical_flop(BEL: HFF), output_port_z_reg[0](BEL: HFF2), " +
"output_port_z_reg[1](BEL: GFF2), processor/data_path_loop[5].arith_logical_flop(BEL: FFF), output_port_z_reg[2](BEL: FFF2), " +
"processor/data_path_loop[4].arith_logical_flop(BEL: EFF), processor/data_path_loop[6].arith_logical_flop(BEL: GFF)]",
DesignTools.getConnectedCells(spi).toString());
}
}

@Test
public void testGetConnectedBELPins() {
Design design = RapidWrightDCP.loadDCP("picoblaze_ooc_X10Y235.dcp");
SiteInst si = design.getSiteInstFromSiteName("SLICE_X15Y238");
{
SitePinInst spi = si.getSitePinInst("E3");
Assertions.assertEquals("[E6LUT.A3, E5LUT.A3]",
DesignTools.getConnectedBELPins(spi).toString());
}
{
SitePinInst spi = si.getSitePinInst("E6");
Assertions.assertEquals("[E6LUT.A6]", DesignTools.getConnectedBELPins(spi).toString());
}
{
SitePinInst spi = si.getSitePinInst("D_I");
Assertions.assertEquals("[DFF2.D]", DesignTools.getConnectedBELPins(spi).toString());
}
{
SitePinInst spi = si.getSitePinInst("CKEN2");
Assertions.assertEquals("[DFF2.CE]", DesignTools.getConnectedBELPins(spi).toString());
}
{
DesignTools.createMissingSitePinInsts(design, design.getNet("clk"));
SitePinInst spi = si.getSitePinInst("CLK2");
Assertions.assertEquals("[EFF.CLK, GFF2.CLK, GFF.CLK, FFF.CLK, HFF2.CLK, HFF.CLK, EFF2.CLK, FFF2.CLK]",
DesignTools.getConnectedBELPins(spi).toString());
}
}
}