Skip to content

RapidWright 2022.2.3-beta Release
Compare
Choose a tag to compare
@clavin-xlnx clavin-xlnx released this 03 May 21:32
· 489 commits to master since this release
v2022.2.3-beta
368002d
This commit was created on GitHub.com and signed with GitHub’s verified signature. The key has expired.
GPG key ID: 4AEE18F83AFDEB23
Expired
Verified
Learn about vigilant mode.

NOTE: Due to GitHub size limitations, All Series7 devices are now located in rapidwright_data2.zip. All other files are in rapidwright_data.zip.

Release Notes:

  • Adds preliminary support for Zstandard compression. Uses it in device cache file generation. Next release will use it for all data files.

  • Fixes an issue with missing Versal Premium families unisim data (#631)

  • Adds an option to the Interchange device model writer to exclude routing info. to enable placement of the largest devices (#658)

  • Fixes an issue in the PBlockGenerator parser (#633)

  • Resolves an issue where collapsed macro ports' parent reference was not set properly (#654)

  • EDIFNetlist.getIOStandard() to inherit IOStandard from EDIFNet (#646)

  • API Additions:

    • com.xilinx.rapidwright.design.Design "public static boolean readEdifAndXdefInParallel()"
    • com.xilinx.rapidwright.design.Design "public static void setReadEdifAndXdefInParallel(boolean readEdifAndXdefInParallel)"
Assets 10
Loading