[RapidWright] Pull in PhysNetlistWriter + RWRoute fixes #53
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Signed-off-by: Eddie Hung <[email protected]>
Signed-off-by: Eddie Hung <[email protected]>
Signed-off-by: Eddie Hung <[email protected]>
Signed-off-by: Eddie Hung <[email protected]>
Signed-off-by: Eddie Hung <[email protected]>
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Signed-off-by: Eddie Hung <[email protected]>
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Notably, pulling in:
[PhysNetlistWriter] Assume static net output BELPins to be sources too RapidWright#929
Fixes various FPGAIF issues with stubs incorrectly appearing on static nets
Fixes an issue with FPGAIF nets associated with differential IOs
Fixes an issue when RWRoute's LUT pin swapping feature is enabled
Fixes an issue where intra-site static routing was being dropped in FPGAIF
Small bugfix in RWRoute which should slightly improve performance
The fixes in Xilinx/RapidWright#928 & Xilinx/RapidWright#929, Xilinx/RapidWright#927 and Xilinx/RapidWright#923 means that an updated set of benchmarks are needed, so this PR temporarily switches over to a staging URL too for the sake of testing.
Note that contestants will need to re-run the DcpToFpgaIF utility on any private benchmarks they may have in order to enjoy the benefits of these fixes too.