examples/ulx3s: serial port demo

.gitignore

@@ -7,3 +7,6 @@ ispTcl.tcl
 ispTcl.tcl.*
 .ispTcl.lock
 work_*/
+.*.d
+.*.swp
+*.log

examples/ulx3s/Makefile

@@ -1,10 +1,40 @@
-all: blinky.bit
+all: blinky.bit hello.bit
 
-blinky.json: blinky.v
-	yosys -p "synth_ecp5 -json blinky.json" blinky.v
+hello.json: pll_120.v
 
-blinky_out.config: blinky.json
-	nextpnr-ecp5 --json blinky.json --textcfg blinky_out.config --45k
+IDCODE ?= 0x21111043 # 12f
 
-blinky.bit: blinky_out.config
-	ecppack blinky_out.config blinky.bit
+%.json: %.v
+	yosys \
+		-p "synth_ecp5 -json $@" \
+		-E .$(basename $@).d \
+		$<
+
+%.config: %.json
+	nextpnr-ecp5 \
+		--json $< \
+		--textcfg $@ \
+		--lpf ulx3s_v20.lpf \
+		--25k
+
+%.bit: %.config
+	ecppack --idcode $(IDCODE) $< $@
+
+%.svf: %.config
+	ecppack --idcode $(IDCODE) --input $< --svf $@
+
+%.flash: %.bit
+	ujprog $<
+%.terminal: %.bit
+	ujprog -t -b 3000000 $<
+
+pll_%.v:
+	../../libtrellis/ecppll \
+		-i 25 \
+		-o $(subst pll_,,$(basename $@)) \
+		-n $(basename $@) \
+		-f $@
+
+clean:
+	$(RM) *.config *.bit .*.d *.svf
+-include .*.d

examples/ulx3s/blinky.v

@@ -1,37 +1,11 @@
-module top(input clk_pin, input btn_pin, output [7:0] led_pin, output gpio0_pin);
-
-    wire clk;
-    wire [7:0] led;
-    wire btn;
-    wire gpio0;
-
-    (* LOC="G2" *) (* IO_TYPE="LVCMOS33" *)
-    TRELLIS_IO #(.DIR("INPUT")) clk_buf (.B(clk_pin), .O(clk));
-
-    (* LOC="R1" *) (* IO_TYPE="LVCMOS33" *)
-    TRELLIS_IO #(.DIR("INPUT")) btn_buf (.B(btn_pin), .O(btn));
-
-    (* LOC="B2" *) (* IO_TYPE="LVCMOS33" *)
-    TRELLIS_IO #(.DIR("OUTPUT")) led_buf_0 (.B(led_pin[0]), .I(led[0]));
-    (* LOC="C2" *) (* IO_TYPE="LVCMOS33" *)
-    TRELLIS_IO #(.DIR("OUTPUT")) led_buf_1 (.B(led_pin[1]), .I(led[1]));
-    (* LOC="C1" *) (* IO_TYPE="LVCMOS33" *)
-    TRELLIS_IO #(.DIR("OUTPUT")) led_buf_2 (.B(led_pin[2]), .I(led[2]));
-    (* LOC="D2" *) (* IO_TYPE="LVCMOS33" *)
-    TRELLIS_IO #(.DIR("OUTPUT")) led_buf_3 (.B(led_pin[3]), .I(led[3]));
-
-    (* LOC="D1" *) (* IO_TYPE="LVCMOS33" *)
-    TRELLIS_IO #(.DIR("OUTPUT")) led_buf_4 (.B(led_pin[4]), .I(led[4]));
-    (* LOC="E2" *) (* IO_TYPE="LVCMOS33" *)
-    TRELLIS_IO #(.DIR("OUTPUT")) led_buf_5 (.B(led_pin[5]), .I(led[5]));
-    (* LOC="E1" *) (* IO_TYPE="LVCMOS33" *)
-    TRELLIS_IO #(.DIR("OUTPUT")) led_buf_6 (.B(led_pin[6]), .I(led[6]));
-    (* LOC="H3" *) (* IO_TYPE="LVCMOS33" *)
-    TRELLIS_IO #(.DIR("OUTPUT")) led_buf_7 (.B(led_pin[7]), .I(led[7]));
-
-
-    (* LOC="L2" *) (* IO_TYPE="LVCMOS33" *)
-    TRELLIS_IO #(.DIR("OUTPUT")) gpio0_buf (.B(gpio0_pin), .I(gpio0));
+module top(
+	input clk_25mhz,
+	input [6:0] btn,
+	output [7:0] led,
+	output wifi_gpio0
+);
+    wire clk = clk_25mhz;
+    wire button = btn[1]; // FIRE1
 
     localparam ctr_width = 24;
     localparam ctr_max = 2**ctr_width - 1;
@@ -40,7 +14,7 @@ module top(input clk_pin, input btn_pin, output [7:0] led_pin, output gpio0_pin)
     reg dir = 0;
 
     always@(posedge clk) begin
-    ctr <= btn ? ctr : (dir ? ctr - 1'b1 : ctr + 1'b1);
+    ctr <= button ? ctr : (dir ? ctr - 1'b1 : ctr + 1'b1);
         if (ctr[ctr_width-1 : ctr_width-3] == 0 && dir == 1)
             dir <= 1'b0;
         else if (ctr[ctr_width-1 : ctr_width-3] == 7 && dir == 0)
@@ -72,6 +46,6 @@ module top(input clk_pin, input btn_pin, output [7:0] led_pin, output gpio0_pin)
     assign led = led_reg;
 
     // Tie GPIO0, keep board from rebooting
-    assign gpio0 = 1'b1;
+    assign wifi_gpio0 = 1'b1;
 
 endmodule

examples/ulx3s/hello.v

@@ -0,0 +1,74 @@
+/*
+ * Hello world on the ulx3s FTDI serial port at 3000000 baud.
+ */
+`default_nettype none
+`include "uart.v"
+`include "pll_120.v"
+
+module top(
+	input clk_25mhz,
+	output [7:0] led,
+	output wifi_gpio0,
+	input ftdi_txd, // from the ftdi chip
+	output ftdi_rxd, // to the ftdi chip
+);
+    // gpio0 must be tied high to prevent board from rebooting
+    assign wifi_gpio0 = 1;
+
+    reg [7:0] led_reg;
+    assign led = led_reg;
+
+    // Generate a 120 MHz clock from the 25 MHz reference
+    wire clk, locked, reset = !locked;
+    pll_120 pll_120_i(clk_25mhz, clk, locked);
+
+    // send/recv data at on the FTDI port
+    // 120 MHz / 40 == 3 megabaud
+    wire uart_txd_ready;
+    reg [7:0] uart_txd;
+    reg uart_txd_strobe;
+    wire uart_rxd_strobe;
+    wire [7:0] uart_rxd;
+
+    uart #(.DIVISOR(40)) uart_i(
+	.clk(clk),
+	.reset(reset),
+	// physical interface
+	.serial_txd(ftdi_rxd), // fpga --> ftdi
+	.serial_rxd(ftdi_txd), // fpga <-- ftdi
+	// logical interface
+	.txd(uart_txd),
+	.txd_ready(uart_txd_ready),
+	.txd_strobe(uart_txd_strobe),
+	.rxd(uart_rxd),
+	.rxd_strobe(uart_rxd_strobe),
+    );
+
+    reg [31:0] counter;
+
+    always @(posedge clk)
+    begin
+	uart_txd_strobe <= 0;
+	counter <= counter + 1;
+
+	if (reset) begin
+		counter <= 0;
+	end else
+	if (uart_rxd_strobe)
+	begin
+		// echo any input on the serial port back to the serial port
+		led_reg <= uart_rxd;
+		uart_txd <= uart_rxd;
+		uart_txd_strobe <= 1;
+	end else
+	if (counter[26:0] == 0
+	&& uart_txd_ready
+	&& !uart_txd_strobe)
+	begin
+		// periodically print an increasing counter on the serial port
+		led_reg <= counter[31:23];
+		uart_txd <= "0" + counter[31:27];
+		uart_txd_strobe <= 1;
+	end
+    end
+endmodule

examples/ulx3s/uart.v

@@ -0,0 +1,175 @@
+`ifndef _uart_v_
+`define _uart_v_
+ /*
+  * This module is designed a 3 Mbaud serial port.
+  * This is the highest data rate supported by
+  * the popular FT232 USB-to-serial chip.
+  *
+  * Copyright (C) 2009 Micah Dowty
+  *           (C) 2018 Trammell Hudson
+  *
+  * Permission is hereby granted, free of charge, to any person obtaining a copy
+  * of this software and associated documentation files (the "Software"), to deal
+  * in the Software without restriction, including without limitation the rights
+  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+  * copies of the Software, and to permit persons to whom the Software is
+  * furnished to do so, subject to the following conditions:
+  *
+  * The above copyright notice and this permission notice shall be included in
+  * all copies or substantial portions of the Software.
+  *
+  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+  * THE SOFTWARE.
+  */
+
+
+`include "util.v"
+
+module uart_tx(
+	input clk,
+	input reset,
+	output serial,
+	output reg ready,
+	input [7:0] data,
+	input data_strobe
+);
+   parameter DIVISOR = 100;
+   wire baud_x1;
+   divide_by_n #(.N(DIVISOR)) baud_x1_div(clk, reset, baud_x1);
+
+   reg [7+1+1:0]   shiftreg;
+   reg         serial_r;
+   assign      serial = !serial_r;
+
+   always @(posedge clk)
+     if (reset) begin
+        shiftreg <= 0;
+        serial_r <= 0;
+     end
+     else if (data_strobe) begin
+        shiftreg <= {
+		1'b1, // stop bit
+		data,
+		1'b0  // start bit (inverted)
+	};
+	ready <= 0;
+     end
+     else if (baud_x1) begin
+        if (shiftreg == 0)
+	begin
+          /* Idle state is idle high, serial_r is inverted */
+          serial_r <= 0;
+	  ready <= 1;
+	end else
+          serial_r <= !shiftreg[0];
+  	// shift the output register down
+        shiftreg <= {1'b0, shiftreg[7+1+1:1]};
+    end else
+    	ready <= (shiftreg == 0);
+
+endmodule
+
+
+module uart_rx(
+	input clk,
+	input reset,
+	input serial,
+	output [7:0] data,
+	output data_strobe
+);
+   parameter DIVISOR = 25; // should the 1/4 the uart_tx divisor
+   wire baud_x4;
+   divide_by_n #(.N(DIVISOR)) baud_x4_div(clk, reset, baud_x4);
+
+   // Clock crossing into clk domain
+   reg [1:0] serial_buf;
+   wire serial_sync = serial_buf[1];
+   always @(posedge clk)
+	serial_buf <= { serial_buf[0], serial };
+
+   /*
+    * State machine: Four clocks per bit, 10 total bits.
+    */
+   reg [8:0]    shiftreg;
+   reg [5:0]    state;
+   reg          data_strobe;
+   wire [3:0]   bit_count = state[5:2];
+   wire [1:0]   bit_phase = state[1:0];
+
+   wire         sampling_phase = (bit_phase == 1);
+   wire         start_bit = (bit_count == 0 && sampling_phase);
+   wire         stop_bit = (bit_count == 9 && sampling_phase);
+
+   wire         waiting_for_start = (state == 0 && serial_sync == 1);
+
+   wire         error = ( (start_bit && serial_sync == 1) ||
+                          (stop_bit && serial_sync == 0) );
+
+   assign       data = shiftreg[7:0];
+
+   always @(posedge clk or posedge reset)
+     if (reset) begin
+        state <= 0;
+        data_strobe <= 0;
+     end
+     else if (baud_x4) begin
+
+        if (waiting_for_start || error || stop_bit)
+          state <= 0;
+        else
+          state <= state + 1;
+
+        if (bit_phase == 1)
+          shiftreg <= { serial_sync, shiftreg[8:1] };
+
+        data_strobe <= stop_bit && !error;
+
+     end
+     else begin
+        data_strobe <= 0;
+     end
+
+endmodule
+
+
+module uart(
+	input clk,
+	input reset,
+	// physical interface
+	input serial_rxd,
+	output serial_txd,
+
+	// logical interface
+	output [7:0] rxd,
+	output rxd_strobe,
+	input [7:0] txd,
+	input txd_strobe,
+	output txd_ready
+);
+	// todo: rx/tx could share a single clock
+	parameter DIVISOR = 40; // must be divisible by 4 for rx clock
+
+	uart_rx #(.DIVISOR(DIVISOR/4)) rx(
+		.clk(clk),
+		.reset(reset),
+		.serial(serial_rxd),
+		.data_strobe(rxd_strobe),
+		.data(rxd),
+	);
+
+	uart_tx #(.DIVISOR(DIVISOR)) tx(
+		.clk(clk),
+		.reset(reset),
+		.serial(serial_txd),
+		.data(txd),
+		.data_strobe(txd_strobe),
+		.ready(txd_ready),
+	);
+endmodule
+
+`endif