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[MSP430] Print add x,x as rla x #57

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[MSP430] Print add x,x as rla x #57

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37 changes: 37 additions & 0 deletions src/llvm/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -27,10 +27,47 @@ using namespace llvm;
#define PRINT_ALIAS_INSTR
#include "MSP430GenAsmWriter.inc"

static bool isRLAmInstruction(const MCInst *MI) {
// add x,x == rla x
unsigned Opc = MI->getOpcode();
if (Opc != MSP430::ADD8mm && Opc != MSP430::ADD16mm &&
Opc != MSP430::ADDC8mm && Opc != MSP430::ADDC16mm)
return false;

// Check operands pairs are equal
const MCOperand &Op1 = MI->getOperand(0);
const MCOperand &Op2 = MI->getOperand(1);
const MCOperand &Op3 = MI->getOperand(2);
const MCOperand &Op4 = MI->getOperand(3);

if (Op1.isReg() && Op3.isReg() && Op1.getReg() == Op3.getReg() &&
Op2.isImm() && Op4.isImm() && Op2.getImm() == Op4.getImm())
return true;
// TODO: Is it possible to check if two MCExpr are equal?
return false;
}

void MSP430InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
StringRef Annot, const MCSubtargetInfo &STI) {
// Print add x,x -> rla x (only mm case here, rr is handled by tablegen)
// TODO: Is it possible to resolve this by tablegen as well?
if (isRLAmInstruction(MI)) {
switch (MI->getOpcode()) {
case MSP430::ADD8mm: O << "\trla.b\t"; break;
case MSP430::ADD16mm: O << "\trla\t"; break;
case MSP430::ADDC8mm: O << "\trlc.b\t"; break;
case MSP430::ADDC16mm: O << "\trlc\t"; break;
default:
llvm_unreachable("Unexpected instruction");
}
printSrcMemOperand(MI, 0, O);
printAnnotation(O, Annot);
return;
}

if (!printAliasInstr(MI, O))
printInstruction(MI, O);

printAnnotation(O, Annot);
}

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10 changes: 5 additions & 5 deletions src/llvm/lib/Target/MSP430/MSP430InstrInfo.td
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Expand Up @@ -590,16 +590,16 @@ def INV16r : InstAlias<"inv\t$dst", (XOR16rc GR16:$dst, -1)>;
def INV8m : InstAlias<"inv.b\t$dst", (XOR8mc memdst:$dst, -1)>;
def INV16m : InstAlias<"inv\t$dst", (XOR16mc memdst:$dst, -1)>;

// printAliasInstr() doesn't check $dst operands are actually equal
// printAliasInstr() doesn't check non-register operands are actually equal
// for RLA and RLC aliases below, so disable printing aliases.

def RLA8r : InstAlias<"rla.b\t$dst", (ADD8rr GR8:$dst, GR8:$dst), 0>;
def RLA16r : InstAlias<"rla\t$dst", (ADD16rr GR16:$dst, GR16:$dst), 0>;
def RLA8r : InstAlias<"rla.b\t$dst", (ADD8rr GR8:$dst, GR8:$dst), 1>;
def RLA16r : InstAlias<"rla\t$dst", (ADD16rr GR16:$dst, GR16:$dst), 1>;
def RLA8m : InstAlias<"rla.b\t$dst", (ADD8mm memdst:$dst, memdst:$dst), 0>;
def RLA16m : InstAlias<"rla\t$dst", (ADD16mm memdst:$dst, memdst:$dst), 0>;

def RLC8r : InstAlias<"rlc.b\t$dst", (ADDC8rr GR8:$dst, GR8:$dst), 0>;
def RLC16r : InstAlias<"rlc\t$dst", (ADDC16rr GR16:$dst, GR16:$dst), 0>;
def RLC8r : InstAlias<"rlc.b\t$dst", (ADDC8rr GR8:$dst, GR8:$dst), 1>;
def RLC16r : InstAlias<"rlc\t$dst", (ADDC16rr GR16:$dst, GR16:$dst), 1>;
def RLC8m : InstAlias<"rlc.b\t$dst", (ADDC8mm memdst:$dst, memdst:$dst), 0>;
def RLC16m : InstAlias<"rlc\t$dst", (ADDC16mm memdst:$dst, memdst:$dst), 0>;

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2 changes: 1 addition & 1 deletion src/llvm/test/CodeGen/MSP430/jumptable.ll
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Expand Up @@ -15,7 +15,7 @@ entry:
%i.addr = alloca i16, align 2
store i16 %i, i16* %i.addr, align 2
%0 = load i16, i16* %i.addr, align 2
; CHECK: add r12, r12
; CHECK: rla r12
; CHECK-NEXT: br .LJTI0_0(r12)
switch i16 %0, label %sw.default [
i16 0, label %sw.bb
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8 changes: 4 additions & 4 deletions src/llvm/test/CodeGen/MSP430/shifts.ll
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Expand Up @@ -22,7 +22,7 @@ entry:
define zeroext i8 @shl8(i8 zeroext %a, i8 zeroext %cnt) nounwind readnone {
entry:
; CHECK: shl8
; CHECK: add.b
; CHECK: rla.b
%shl = shl i8 %a, %cnt
ret i8 %shl
}
Expand All @@ -47,7 +47,7 @@ entry:
define zeroext i16 @shl16(i16 zeroext %a, i16 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: shl16:
; CHECK: add
; CHECK: rla
%shl = shl i16 %a, %cnt
ret i16 %shl
}
Expand Down Expand Up @@ -80,8 +80,8 @@ entry:
; CHECK-LABEL: lshl10_i16:
; CHECK: mov.b r12, r12
; CHECK-NEXT: swpb r12
; CHECK-NEXT: add r12, r12
; CHECK-NEXT: add r12, r12
; CHECK-NEXT: rla r12
; CHECK-NEXT: rla r12
%shl = shl i16 %a, 10
ret i16 %shl
}
4 changes: 2 additions & 2 deletions src/llvm/test/MC/MSP430/opcode.s
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Expand Up @@ -125,9 +125,9 @@
;; Emulated logical instructions
inv r7 ; CHECK-INST: inv r7
; CHECK: encoding: [0x37,0xe3]
rla r7 ; CHECK-INST: add r7, r7
rla r7 ; CHECK-INST: rla r7
; CHECK: encoding: [0x07,0x57]
rlc r7 ; CHECK-INST: addc r7, r7
rlc r7 ; CHECK-INST: rlc r7
; CHECK: encoding: [0x07,0x67]

;; Emulated program flow control instructions
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