Add a number of additional APIs to the various SIMD accelerated vecto…

…r types (dotnet#111179) * Add a number of additional APIs to the various SIMD accelerated vector types * Add tests for the new vector APIs * Fix the boolean logic for the vectorized IsEvenInteger * Try to fix the Mono build * Fixing some RyuJIT handling * Add some additional Mono handling and document what's hindering other support * Update src/libraries/System.Private.CoreLib/src/System/Half.cs * Fix mono interp * Ensure the handling of the Vector2/3 All/Any/None and Count/IndexOf/LastIndexOf methods is correct * Try and fix the mono build * Don't accelerate the new methods for Vector2/3 on Mono * Fix mono build warning * Ensure the right class name is resolved for Vector4
adamsitnik · Jan 16, 2025 · 1af7c23 · 1af7c23
1 parent 5048656
commit 1af7c23
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diff --git a/src/coreclr/jit/compiler.h b/src/coreclr/jit/compiler.h
@@ -3377,6 +3377,26 @@ class Compiler
                                    CorInfoType simdBaseJitType,
                                    unsigned    simdSize);
 
+    GenTree* gtNewSimdIsEvenIntegerNode(var_types   type,
+                                        GenTree*    op1,
+                                        CorInfoType simdBaseJitType,
+                                        unsigned    simdSize);
+
+    GenTree* gtNewSimdIsFiniteNode(var_types   type,
+                                   GenTree*    op1,
+                                   CorInfoType simdBaseJitType,
+                                   unsigned    simdSize);
+
+    GenTree* gtNewSimdIsInfinityNode(var_types   type,
+                                     GenTree*    op1,
+                                     CorInfoType simdBaseJitType,
+                                     unsigned    simdSize);
+
+    GenTree* gtNewSimdIsIntegerNode(var_types   type,
+                                    GenTree*    op1,
+                                    CorInfoType simdBaseJitType,
+                                    unsigned    simdSize);
+
     GenTree* gtNewSimdIsNaNNode(var_types   type,
                                 GenTree*    op1,
                                 CorInfoType simdBaseJitType,
@@ -3387,6 +3407,21 @@ class Compiler
                                      CorInfoType simdBaseJitType,
                                      unsigned    simdSize);
 
+    GenTree* gtNewSimdIsNegativeInfinityNode(var_types   type,
+                                             GenTree*    op1,
+                                             CorInfoType simdBaseJitType,
+                                             unsigned    simdSize);
+
+    GenTree* gtNewSimdIsNormalNode(var_types   type,
+                                   GenTree*    op1,
+                                   CorInfoType simdBaseJitType,
+                                   unsigned    simdSize);
+
+    GenTree* gtNewSimdIsOddIntegerNode(var_types   type,
+                                       GenTree*    op1,
+                                       CorInfoType simdBaseJitType,
+                                       unsigned    simdSize);
+
     GenTree* gtNewSimdIsPositiveNode(var_types   type,
                                      GenTree*    op1,
                                      CorInfoType simdBaseJitType,
@@ -3397,6 +3432,11 @@ class Compiler
                                              CorInfoType simdBaseJitType,
                                              unsigned    simdSize);
 
+    GenTree* gtNewSimdIsSubnormalNode(var_types   type,
+                                      GenTree*    op1,
+                                      CorInfoType simdBaseJitType,
+                                      unsigned    simdSize);
+
     GenTree* gtNewSimdIsZeroNode(var_types   type,
                                  GenTree*    op1,
                                  CorInfoType simdBaseJitType,