Fixes esil xL xH swapped registers for udis

alvarofe · Jul 20, 2015 · 1122bc1 · 1122bc1
1 parent 49eaa2a
commit 1122bc1
Showing 1 changed file with 14 additions and 14 deletions.
diff --git a/libr/anal/p/anal_x86_udis.c b/libr/anal/p/anal_x86_udis.c
@@ -585,14 +585,14 @@ static int set_reg_profile(RAnal *anal) {
 		"gpr	ah	.8	24	0\n"
 		"gpr	al	.8	25	0\n"
 		"gpr	bx	.16	0	0\n"
-		"gpr	bh	.8	0	0\n"
-		"gpr	bl	.8	1	0\n"
+		"gpr	bh	.8	1	0\n"
+		"gpr	bl	.8	0	0\n"
 		"gpr	cx	.16	4	0\n"
-		"gpr	ch	.8	4	0\n"
-		"gpr	cl	.8	5	0\n"
+		"gpr	ch	.8	5	0\n"
+		"gpr	cl	.8	4	0\n"
 		"gpr	dx	.16	8	0\n"
-		"gpr	dh	.8	8	0\n"
-		"gpr	dl	.8	9	0\n"
+		"gpr	dh	.8	9	0\n"
+		"gpr	dl	.8	8	0\n"
 		"gpr	sp	.16	60	0\n"
 		"gpr	bp	.16	20	0\n"
 		"gpr	si	.16	12	0\n"
@@ -637,16 +637,16 @@ static int set_reg_profile(RAnal *anal) {
 		"gpr	al	.8	25	0\n"
 		"gpr	ebx	.32	0	0\n"
 		"gpr	bx	.16	0	0\n"
-		"gpr	bh	.8	0	0\n"
-		"gpr	bl	.8	1	0\n"
+		"gpr	bh	.8	1	0\n"
+		"gpr	bl	.8	0	0\n"
 		"gpr	ecx	.32	4	0\n"
 		"gpr	cx	.16	4	0\n"
-		"gpr	ch	.8	4	0\n"
-		"gpr	cl	.8	5	0\n"
+		"gpr	ch	.8	5	0\n"
+		"gpr	cl	.8	4	0\n"
 		"gpr	edx	.32	8	0\n"
 		"gpr	dx	.16	8	0\n"
-		"gpr	dh	.8	8	0\n"
-		"gpr	dl	.8	9	0\n"
+		"gpr	dh	.8	9	0\n"
+		"gpr	dl	.8	8	0\n"
 		"gpr	esp	.32	60	0\n"
 		"gpr	sp	.16	60	0\n"
 		"gpr	ebp	.32	20	0\n"
@@ -699,8 +699,8 @@ static int set_reg_profile(RAnal *anal) {
 		 "gpr	rbx	.64	40	0\n"
 		 "gpr	ebx	.32	40	0\n"
 		 "gpr	bx	.16	40	0\n"
-		 "gpr	bh	.8	40	0\n"
-		 "gpr	bl	.8	41	0\n"
+		 "gpr	bh	.8	41	0\n"
+		 "gpr	bl	.8	40	0\n"
 		 "gpr	r11	.64	48	0\n"
 		 "gpr	r10	.64	56	0\n"
 		 "gpr	r9	.64	64	0\n"