VLSI Design Assignment given during the course, where we were supposed to make AND, OR, XOR logic gates and Ring gate in Verilog and NGspice, and then, make the layout in MAGIC software.
Project required us to make a 4-bit carry look ahead (CLA) adder by building generate, propagate, carry and sum blocks, individually. This included combining the AND, OR, NOT and XOR gates previously made in the assignment, to form a well-formed adder.