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Signed-off-by: Michal Czyz <[email protected]>
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# Copyright 2025 bazel_rules_hdl Authors | ||
# | ||
# Licensed under the Apache License, Version 2.0 (the "License"); | ||
# you may not use this file except in compliance with the License. | ||
# You may obtain a copy of the License at | ||
# | ||
# http://www.apache.org/licenses/LICENSE-2.0 | ||
# | ||
# Unless required by applicable law or agreed to in writing, software | ||
# distributed under the License is distributed on an "AS IS" BASIS, | ||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
# See the License for the specific language governing permissions and | ||
# limitations under the License. | ||
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load("@rules_cc//cc:defs.bzl", "cc_test") | ||
load("//vcs:defs.bzl", "vcs_binary", "vcs_run") | ||
load("//verilog:defs.bzl", "verilog_library") | ||
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package( | ||
default_applicable_licenses = ["//:package_license"], | ||
default_visibility = ["//visibility:private"], | ||
) | ||
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verilog_library( | ||
name = "adder", | ||
srcs = [ | ||
"adder.sv", | ||
], | ||
) | ||
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verilog_library( | ||
name = "tb", | ||
srcs = [ | ||
"tb.sv", | ||
], | ||
deps = [ | ||
":adder", | ||
], | ||
) | ||
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vcs_binary( | ||
name = "tb_vcs", | ||
vcs_env = "//vcs/tests:vcs_env.sh", | ||
module = ":tb", | ||
module_top = "tb", | ||
opts = [ | ||
"-full64", | ||
"+vcs+lic+wait", | ||
"+error+500", | ||
], | ||
visibility = [ | ||
"//visibility:public", | ||
], | ||
) | ||
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vcs_run( | ||
name = "tb_vcs_run", | ||
binary = ":tb_vcs", | ||
trace = True, | ||
visibility = [ | ||
"//visibility:public", | ||
], | ||
) |
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# VCS test | ||
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You need to update variables in the `vcs_env.sh` file before running the tests. |
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// Copyright 2025 bazel_rules_hdl Authors | ||
// | ||
//Licensed under the Apache License, Version 2.0 (the "License"); | ||
//you may not use this file except in compliance with the License. | ||
//You may obtain a copy of the License at | ||
// | ||
// http://www.apache.org/licenses/LICENSE-2.0 | ||
// | ||
//Unless required by applicable law or agreed to in writing, software | ||
//distributed under the License is distributed on an "AS IS" BASIS, | ||
//WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
//See the License for the specific language governing permissions and | ||
//limitations under the License. | ||
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module adder ( | ||
input [7:0] x, | ||
input [7:0] y, | ||
input carry_in, | ||
output carry_output_bit, | ||
output [7:0] sum | ||
); | ||
logic [8:0] result; | ||
/* verilator lint_off WIDTH */ | ||
assign result = x + y + carry_in; | ||
/* verilator lint_on WIDTH */ | ||
assign sum = result[7:0]; | ||
assign carry_output_bit = result[8]; | ||
endmodule |
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// Copyright 2025 bazel_rules_hdl Authors | ||
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module tb (); | ||
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// Waveform | ||
initial begin : proc_waveform | ||
string vcd_file = "dump.vcd"; | ||
if ($value$plusargs("vcd=%s", vcd_file)) begin | ||
$display(vcd_file); | ||
$dumpfile(vcd_file); | ||
$dumpvars(); | ||
end | ||
end | ||
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// DUT | ||
logic [7:0] x; | ||
logic [7:0] y; | ||
logic carry_in; | ||
logic carry_output_bit; | ||
logic [7:0] sum; | ||
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adder dut ( | ||
.x(x), | ||
.y(y), | ||
.carry_in(carry_in), | ||
.carry_output_bit(carry_output_bit), | ||
.sum(sum) | ||
); | ||
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// Test procedure | ||
initial begin : proc_test | ||
x = 0; | ||
y = 0; | ||
carry_in = 0; | ||
$display("Testing adder:"); | ||
#10 x = 1; | ||
y = 2; | ||
#10 $display("x=%d, y=%d, x+y=%d", x, y, sum); | ||
assert (sum == 3); | ||
#10 $display("Testing done."); | ||
$finish(); | ||
end | ||
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endmodule |
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#!/bin/bash | ||
# Copyright 2025 bazel_rules_hdl Authors | ||
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export LM_LICENSE_FILE=<lm_license_file> | ||
export VCS_HOME=<vcs_home> | ||
export PATH=$VCS_HOME/bin:$PATH |