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Fix VCS VCD generation
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Signed-off-by: Michal Czyz <[email protected]>
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mczyz-antmicro committed Jan 7, 2025
1 parent cf0f335 commit 4e0c889
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Showing 6 changed files with 147 additions and 1 deletion.
2 changes: 1 addition & 1 deletion vcs/defs.bzl
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Expand Up @@ -144,7 +144,7 @@ def _vcs_run(ctx):
# Waveform
if ctx.attr.trace:
trace_file = ctx.actions.declare_file("{}.vcd".format(ctx.label.name))
args.extend(["-vcd", trace_file.path])
args.extend(["+vcd="+trace_file.path])
args.append("+vcs+dumpon+0+0")
args.append("+vcs+dumparrays")
outputs.append(trace_file)
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64 changes: 64 additions & 0 deletions vcs/tests/BUILD
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# Copyright 2025 bazel_rules_hdl Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

load("@rules_cc//cc:defs.bzl", "cc_test")
load("//vcs:defs.bzl", "vcs_binary", "vcs_run")
load("//verilog:defs.bzl", "verilog_library")

package(
default_applicable_licenses = ["//:package_license"],
default_visibility = ["//visibility:private"],
)

verilog_library(
name = "adder",
srcs = [
"adder.sv",
],
)


verilog_library(
name = "tb",
srcs = [
"tb.sv",
],
deps = [
":adder",
],
)

vcs_binary(
name = "tb_vcs",
vcs_env = "//vcs/tests:vcs_env.sh",
module = ":tb",
module_top = "tb",
opts = [
"-full64",
"+vcs+lic+wait",
"+error+500",
],
visibility = [
"//visibility:public",
],
)

vcs_run(
name = "tb_vcs_run",
binary = ":tb_vcs",
trace = True,
visibility = [
"//visibility:public",
],
)
3 changes: 3 additions & 0 deletions vcs/tests/README.md
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# VCS test

You need to update variables in the `vcs_env.sh` file before running the tests.
29 changes: 29 additions & 0 deletions vcs/tests/adder.sv
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// Copyright 2025 bazel_rules_hdl Authors
//
//Licensed under the Apache License, Version 2.0 (the "License");
//you may not use this file except in compliance with the License.
//You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
//Unless required by applicable law or agreed to in writing, software
//distributed under the License is distributed on an "AS IS" BASIS,
//WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
//See the License for the specific language governing permissions and
//limitations under the License.


module adder (
input [7:0] x,
input [7:0] y,
input carry_in,
output carry_output_bit,
output [7:0] sum
);
logic [8:0] result;
/* verilator lint_off WIDTH */
assign result = x + y + carry_in;
/* verilator lint_on WIDTH */
assign sum = result[7:0];
assign carry_output_bit = result[8];
endmodule
44 changes: 44 additions & 0 deletions vcs/tests/tb.sv
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// Copyright 2025 bazel_rules_hdl Authors

module tb ();

// Waveform
initial begin : proc_waveform
string vcd_file = "dump.vcd";
if ($value$plusargs("vcd=%s", vcd_file)) begin
$display(vcd_file);
$dumpfile(vcd_file);
$dumpvars();
end
end

// DUT
logic [7:0] x;
logic [7:0] y;
logic carry_in;
logic carry_output_bit;
logic [7:0] sum;

adder dut (
.x(x),
.y(y),
.carry_in(carry_in),
.carry_output_bit(carry_output_bit),
.sum(sum)
);

// Test procedure
initial begin : proc_test
x = 0;
y = 0;
carry_in = 0;
$display("Testing adder:");
#10 x = 1;
y = 2;
#10 $display("x=%d, y=%d, x+y=%d", x, y, sum);
assert (sum == 3);
#10 $display("Testing done.");
$finish();
end

endmodule
6 changes: 6 additions & 0 deletions vcs/tests/vcs_env.sh
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#!/bin/bash
# Copyright 2025 bazel_rules_hdl Authors

export LM_LICENSE_FILE=<lm_license_file>
export VCS_HOME=<vcs_home>
export PATH=$VCS_HOME/bin:$PATH

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