P&R: Add option to enable/disable improve_placement

Some designs fail on during resize script. This script runs `detailed_placement` followed by `improve_placement` command. I've noticed that `improve_placement` causes some cell to either be place to close together triggering overlap warning or they truly overlapped. I checked overlapping reports using OpenROAD GUI interface. Signed-off-by: Maciej Dudek <[email protected]>
antmicro · Dec 14, 2023 · ccb553b · ccb553b
1 parent cfe6f62
commit ccb553b
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diff --git a/place_and_route/build_defs.bzl b/place_and_route/build_defs.bzl
@@ -105,5 +105,6 @@ place_and_route = rule(
         "sink_clustering_size": attr.int(doc = "Clock tree synthesis sink group size"),
         "sink_clustering_max_diameter": attr.int(doc = "Clock tree synthesis sink group desired diamater in microns"),
         "min_pin_distance": attr.string(doc = "The minimum distance in microns between pins around the outside of the block."),
+        "enable_improve_placement": attr.bool(default=True, doc = "Enable/Disable improve_placement pass.")
     },
 )
diff --git a/place_and_route/private/resize.bzl b/place_and_route/private/resize.bzl
@@ -51,7 +51,7 @@ def resize(ctx, open_road_info):
         ),
     ] + placement_padding_struct.commands + [
         "detailed_placement",
-        "improve_placement",
+        "improve_placement" if ctx.attr.enable_improve_placement else "",
         "optimize_mirroring",
         "check_placement -verbose",
         "report_checks -path_delay min_max -format full_clock_expanded -fields {input_pin slew capacitance} -digits 3",