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[TIR] VNNI and ARM dot product intrinsic for tensorization #10925
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# Licensed to the Apache Software Foundation (ASF) under one | ||
# or more contributor license agreements. See the NOTICE file | ||
# distributed with this work for additional information | ||
# regarding copyright ownership. The ASF licenses this file | ||
# to you under the Apache License, Version 2.0 (the | ||
# "License"); you may not use this file except in compliance | ||
# with the License. You may obtain a copy of the License at | ||
# | ||
# http://www.apache.org/licenses/LICENSE-2.0 | ||
# | ||
# Unless required by applicable law or agreed to in writing, | ||
# software distributed under the License is distributed on an | ||
# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY | ||
# KIND, either express or implied. See the License for the | ||
# specific language governing permissions and limitations | ||
# under the License. | ||
# pylint: disable=unused-import | ||
"""Intrinsics for tensorization.""" | ||
from .x86 import * | ||
from .arm_cpu import * |
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# Licensed to the Apache Software Foundation (ASF) under one | ||||
# or more contributor license agreements. See the NOTICE file | ||||
# distributed with this work for additional information | ||||
# regarding copyright ownership. The ASF licenses this file | ||||
# to you under the Apache License, Version 2.0 (the | ||||
# "License"); you may not use this file except in compliance | ||||
# with the License. You may obtain a copy of the License at | ||||
# | ||||
# http://www.apache.org/licenses/LICENSE-2.0 | ||||
# | ||||
# Unless required by applicable law or agreed to in writing, | ||||
# software distributed under the License is distributed on an | ||||
# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY | ||||
# KIND, either express or implied. See the License for the | ||||
# specific language governing permissions and limitations | ||||
# under the License. | ||||
# pylint: disable=invalid-name,missing-function-docstring | ||||
"""Intrinsics for ARM tensorization.""" | ||||
from tvm.script import tir as T | ||||
from .. import TensorIntrin | ||||
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# TODO(masahi): Parametrize the TVMScript description of dot product by | ||||
# shape and dtype, and share the common description with x86. | ||||
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@T.prim_func | ||||
def dot_product_4x4_i8i8i32_desc( | ||||
A: T.Buffer((4,), "int8", offset_factor=1), | ||||
B: T.Buffer((4, 4), "int8", offset_factor=1), | ||||
C: T.Buffer((4,), "int32", offset_factor=1), | ||||
) -> None: | ||||
with T.block("root"): | ||||
T.reads(C[0:4], A[0:4], B[0:4, 0:4]) | ||||
T.writes(C[0:4]) | ||||
for i in T.serial(0, 4): | ||||
with T.init(): | ||||
C[i] = T.int32(0) | ||||
for k in T.serial(0, 4): | ||||
with T.block("update"): | ||||
vi, vk = T.axis.remap("SR", [i, k]) | ||||
C[vi] = C[vi] + T.cast(A[vk], "int32") * T.cast(B[vi, vk], "int32") | ||||
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@T.prim_func | ||||
def dot_product_4x4_i8i8i32_neon( | ||||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. This is equivalent to the TE one in tvm/python/tvm/topi/arm_cpu/tensor_intrin.py Line 536 in 912993f
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A: T.Buffer((4,), "int8", offset_factor=1), | ||||
B: T.Buffer((4, 4), "int8", offset_factor=1), | ||||
C: T.Buffer((4,), "int32", offset_factor=1), | ||||
) -> None: | ||||
with T.block("root"): | ||||
T.reads(C[0:4], A[0:4], B[0:4, 0:4]) | ||||
T.writes(C[0:4]) | ||||
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A_int8 = A.vload([0], "int8x4") | ||||
re_int32 = T.reinterpret(A_int8, dtype="int32") | ||||
vec_ai32 = T.broadcast(re_int32, 2) | ||||
vec_a = T.reinterpret(vec_ai32, dtype="int8x8") | ||||
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vec_b = B.vload([0, 0], dtype="int8x16") | ||||
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# TODO(masahi): Remove duplication when inlined function call is supported | ||||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. cc @junrushao1994 @yelite, I want to define and call a convenience function like tvm/python/tvm/topi/arm_cpu/tensor_intrin.py Line 625 in 912993f
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Yes, it is likely doable and @Hzfengsy probably already has something ready |
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vec_b_low = T.vectorlow(vec_b, dtype="int8x8") | ||||
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multiply_low = T.call_llvm_pure_intrin( | ||||
T.llvm_lookup_intrinsic_id("llvm.aarch64.neon.smull.v8i16"), | ||||
T.uint32(2), | ||||
vec_a, | ||||
vec_b_low, | ||||
dtype="int16x8", | ||||
) | ||||
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pairwise_reduction_low = T.call_llvm_pure_intrin( | ||||
T.llvm_lookup_intrinsic_id("llvm.aarch64.neon.saddlp.v4i32.v8i16"), | ||||
T.uint32(1), | ||||
multiply_low, | ||||
dtype="int32x4", | ||||
) | ||||
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vec_b_high = T.vectorhigh(vec_b, dtype="int8x8") | ||||
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multiply_high = T.call_llvm_pure_intrin( | ||||
T.llvm_lookup_intrinsic_id("llvm.aarch64.neon.smull.v8i16"), | ||||
T.uint32(2), | ||||
vec_a, | ||||
vec_b_high, | ||||
dtype="int16x8", | ||||
) | ||||
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pairwise_reduction_high = T.call_llvm_pure_intrin( | ||||
T.llvm_lookup_intrinsic_id("llvm.aarch64.neon.saddlp.v4i32.v8i16"), | ||||
T.uint32(1), | ||||
multiply_high, | ||||
dtype="int32x4", | ||||
) | ||||
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C[T.ramp(T.int32(0), 1, 4)] += T.call_llvm_pure_intrin( | ||||
T.llvm_lookup_intrinsic_id("llvm.aarch64.neon.addp.v4i32"), | ||||
T.uint32(2), | ||||
pairwise_reduction_low, | ||||
pairwise_reduction_high, | ||||
dtype="int32x4", | ||||
) | ||||
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@T.prim_func | ||||
def dot_product_4x4_i8i8i32_sdot( | ||||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. This is equivalent to the TE one in tvm/python/tvm/topi/arm_cpu/tensor_intrin.py Line 431 in 912993f
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A: T.Buffer((4,), "int8", offset_factor=1), | ||||
B: T.Buffer((4, 4), "int8", offset_factor=1), | ||||
C: T.Buffer((4,), "int32", offset_factor=1), | ||||
) -> None: | ||||
with T.block("root"): | ||||
T.reads(C[0:4], A[0:4], B[0:4, 0:4]) | ||||
T.writes(C[0:4]) | ||||
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A_i8x4 = A.vload([0], "int8x4") | ||||
A_i32 = T.reinterpret(A_i8x4, dtype="int32") | ||||
vec_ai32 = T.broadcast(A_i32, 4) | ||||
vec_a = T.reinterpret(vec_ai32, dtype="int8x16") | ||||
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vec_b = B.vload([0, 0], dtype="int8x16") | ||||
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C[T.ramp(T.int32(0), 1, 4)] += T.call_llvm_pure_intrin( | ||||
T.llvm_lookup_intrinsic_id("llvm.aarch64.neon.sdot.v4i32.v16i8"), | ||||
T.uint32(3), | ||||
T.int32x4(0), | ||||
vec_a, | ||||
vec_b, | ||||
dtype="int32x4", | ||||
) | ||||
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ARM_DOT_4x4_i8_NEON_INTRIN = "dot_4x4_i8i8s32_neon" | ||||
ARM_DOT_4x4_i8_SDOT_INTRIN = "dot_4x4_i8i8s32_sdot" | ||||
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TensorIntrin.register( | ||||
ARM_DOT_4x4_i8_NEON_INTRIN, dot_product_4x4_i8i8i32_desc, dot_product_4x4_i8i8i32_neon | ||||
) | ||||
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TensorIntrin.register( | ||||
ARM_DOT_4x4_i8_SDOT_INTRIN, dot_product_4x4_i8i8i32_desc, dot_product_4x4_i8i8i32_sdot | ||||
) |
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# Licensed to the Apache Software Foundation (ASF) under one | ||||
# or more contributor license agreements. See the NOTICE file | ||||
# distributed with this work for additional information | ||||
# regarding copyright ownership. The ASF licenses this file | ||||
# to you under the Apache License, Version 2.0 (the | ||||
# "License"); you may not use this file except in compliance | ||||
# with the License. You may obtain a copy of the License at | ||||
# | ||||
# http://www.apache.org/licenses/LICENSE-2.0 | ||||
# | ||||
# Unless required by applicable law or agreed to in writing, | ||||
# software distributed under the License is distributed on an | ||||
# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY | ||||
# KIND, either express or implied. See the License for the | ||||
# specific language governing permissions and limitations | ||||
# under the License. | ||||
# pylint: disable=invalid-name,missing-function-docstring | ||||
"""Intrinsics for x86 tensorization.""" | ||||
from tvm.script import tir as T | ||||
from .. import TensorIntrin | ||||
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# Tensorized intrinsic description and VNNI-specific implementation. | ||||
# Equivalent to the ones in topi/x86/tensor_intrin.py | ||||
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@T.prim_func | ||||
def dot_product_16x4_u8i8i32_desc( | ||||
A: T.Buffer((4,), "uint8", offset_factor=1), | ||||
B: T.Buffer((16, 4), "int8", offset_factor=1), | ||||
C: T.Buffer((16,), "int32", offset_factor=1), | ||||
) -> None: | ||||
with T.block("root"): | ||||
T.reads(C[0:16], A[0:4], B[0:16, 0:4]) | ||||
T.writes(C[0:16]) | ||||
for i in T.serial(0, 16): | ||||
with T.init(): | ||||
C[i] = T.int32(0) | ||||
for k in T.serial(0, 4): | ||||
with T.block("update"): | ||||
vi, vk = T.axis.remap("SR", [i, k]) | ||||
C[vi] = C[vi] + T.cast(A[vk], "int32") * T.cast(B[vi, vk], "int32") | ||||
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@T.prim_func | ||||
def dot_product_16x4_u8i8i32_vnni( | ||||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Equivalent to the TE one in tvm/python/tvm/topi/x86/tensor_intrin.py Line 244 in 912993f
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A: T.Buffer((4,), "uint8", offset_factor=1), | ||||
B: T.Buffer((16, 4), "int8", offset_factor=1), | ||||
C: T.Buffer((16,), "int32", offset_factor=1), | ||||
) -> None: | ||||
with T.block("root"): | ||||
T.reads(C[0:16], A[0:4], B[0:16, 0:4]) | ||||
T.writes(C[0:16]) | ||||
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A_u8x4 = A.vload([0], "uint8x4") | ||||
A_i32 = T.reinterpret(A_u8x4, dtype="int32") | ||||
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B_i8x64 = B.vload([0, 0], dtype="int8x64") | ||||
B_i32x16 = T.reinterpret(B_i8x64, dtype="int32x16") | ||||
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C[T.ramp(T.int32(0), 1, 16)] += T.call_llvm_pure_intrin( # Note: this is an update += | ||||
T.llvm_lookup_intrinsic_id("llvm.x86.avx512.vpdpbusd.512"), | ||||
T.uint32(0), | ||||
T.int32x16(0), | ||||
T.broadcast(A_i32, 16), | ||||
B_i32x16, | ||||
dtype="int32x16", | ||||
) | ||||
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VNNI_DOT_16x4_INTRIN = "dot_16x4_vnni" | ||||
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TensorIntrin.register( | ||||
VNNI_DOT_16x4_INTRIN, dot_product_16x4_u8i8i32_desc, dot_product_16x4_u8i8i32_vnni | ||||
) |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
cc @junrushao1994 @yelite, this is one of the common needs for meta programming support in TVMScript. I think shape parameterization is possible via
specialize
, but not sure if I can use that withT.Buffer
syntax sugar.A similar need arises for tensorcore (different mma shape x data type)