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[Hexagon] Add a test to show how to use multi input async dma pipelin… #13110

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merged 8 commits into from
Oct 26, 2022

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nverke
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@nverke nverke commented Oct 17, 2022

…ing.

Just adding an example to show https://github.com/apache/tvm/pull/13037/files addition working for these tests as well.

cc @adstraw

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tvm-bot commented Oct 17, 2022

Thanks for contributing to TVM! Please refer to the contributing guidelines https://tvm.apache.org/docs/contribute/ for useful information and tips. Please request code reviews from Reviewers by @-ing them in a comment.

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@areusch areusch added needs-triage PRs or issues that need to be investigated by maintainers to find the right assignees to address it and removed needs-triage PRs or issues that need to be investigated by maintainers to find the right assignees to address it labels Oct 19, 2022
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Looks really good overall!

sch.compute_at(cache_read_block_b, no)
sch.fuse(*sch.get_loops(cache_read_block_b)[1:])

cache_read_block_c = sch.cache_write(compute_block, 0, "global.vtcm")
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"cache_write_block_c"

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b,
size_a,
expected_output,
use_async_copy=0,
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do you want to enable async_copy by default?

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No, not that it mattered much since other runs dont mark those stages as async anyway though. Just felt more correct to have it as off.

@nverke nverke force-pushed the multi_input_async_dma branch 2 times, most recently from 8eb3278 to 7617c4e Compare October 25, 2022 20:31
@nverke nverke force-pushed the multi_input_async_dma branch from 6d9b5cb to 66127f4 Compare October 26, 2022 16:16
@masahi masahi merged commit 04afd83 into apache:main Oct 26, 2022
xinetzone pushed a commit to daobook/tvm that referenced this pull request Nov 10, 2022
apache#13110)

* [Hexagon] Add a test to show how to use multi input async dma pipelining.

* updates to variable naming and removal of 4.19MB test that fails on 888 devices.

* [Hexagon] Add test cases for adding async dma pipleining to metaschedule generated conv2d.

* Add tests for actual conv2d sourced from resnet50 metascheduling.

* [Hexagon] Change logs.

* Add test to show effect of increased buffer sizes for pipelining.

* skip tests in CI.

* lint
xinetzone pushed a commit to daobook/tvm that referenced this pull request Nov 25, 2022
apache#13110)

* [Hexagon] Add a test to show how to use multi input async dma pipelining.

* updates to variable naming and removal of 4.19MB test that fails on 888 devices.

* [Hexagon] Add test cases for adding async dma pipleining to metaschedule generated conv2d.

* Add tests for actual conv2d sourced from resnet50 metascheduling.

* [Hexagon] Change logs.

* Add test to show effect of increased buffer sizes for pipelining.

* skip tests in CI.

* lint
B_i8x128 = B[0, 0:128]
B_i32x32: T.int32x32 = T.reinterpret(B_i8x128, dtype="int32x32")
C[0:32] = T.call_llvm_pure_intrin(
4217,
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This number doesn't mean anything---those IDs are generated on every build. What intrinsic was this intended to represent?

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yeah we should replace this with T.llvm_lookup_intrinsic_id("llvm.hexagon.V6.vrmpyub.acc.128B") @nverke

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Ahh interesting thought that they were tied to each intrin, will update accordingly!

@nverke nverke deleted the multi_input_async_dma branch January 13, 2023 23:41
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6 participants