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[microNPU] Add unary elementwise operator infrastructure with ABS #9530

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merged 2 commits into from
Nov 22, 2021

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ekalda
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@ekalda ekalda commented Nov 18, 2021

  • Added unary elementwise ABS legalization support and tests
  • Added unary_elementwise Relay to TIR lowering and tests
  • Added TIR to Vela translation and tests
  • Added codegen tests

Co-authored-by: Rishabh Jain [email protected]

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ekalda commented Nov 18, 2021

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Great work @ekalda @jainris :) Just some minor comments

params = self.params_class(post.op.body)
params.ifm.tensor = post.args[0]

if str(params.ofm.layout) != "NHWC":
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IIRC we agreed to remove these checks, please ignore if not

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All the other operators still have these checks so maybe we can remove them in a follow-up patch for all of the operators (or to be precise, I think we need to add some guards into the is_valid() checks to prevent attempting offloading graphs with non-NHWC layout...)

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No worries, I was referring to #9508 (comment) but didn't realize the other operators still had this check, I think a follow up would be fine :)

Comment on lines 782 to 783
while len(unary_input_shape) < 4:
unary_input_shape = [1] + unary_input_shape
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Suggested change
while len(unary_input_shape) < 4:
unary_input_shape = [1] + unary_input_shape
pad_size = 4 - len(unary_input_shape)
unary_input_shape = ([1] * pad_size) + unary_input_shape

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Done

) -> vapi.NpuElementWiseOperation:
"""This function will translate a tir extern_call
as produced by Relay to TIR compilation.
Parameters
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Nit: insert blank line

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Done

quantize arguments
"""

ifm = 0
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Looks like we missed this for binary elementwise also... should we follow convention here and use capitals?

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Done (i.e. changed both to use capitals)

Comment on lines 88 to 89
int ifm_index = 0;
int result_index = 2;
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Better to make these const

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Done

<< operator_type;

auto ifm_dtype = ifm->dtype;
ICHECK(ifm_dtype == DataType::UInt(8) || ifm_dtype == DataType::Int(8))
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Should we use the TypeReporter here instead, similar to other operators?

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Well spotted :)

attrs->ifm_zero_point = ifm_zero_point;
attrs->ofm_scale = ofm_scale;
attrs->ofm_zero_point = ofm_zero_point;
attrs->ofm_channels = ofm_channels;
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Suggested change
attrs->ofm_channels = ofm_channels;
attrs->ofm_channels = std::move(ofm_channels);

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Done

int clip_max, String ifm_layout, String ofm_layout) {
auto attrs = make_object<EthosuUnaryElementwiseAttrs>();

attrs->operator_type = operator_type;
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Suggested change
attrs->operator_type = operator_type;
attrs->operator_type = std::move(operator_type);

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Done

mod, _ = relay.frontend.from_tflite(
tflite_model,
shape_dict={"input": ifm_shape},
dtype_dict={"x": dtype},
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Suggested change
dtype_dict={"x": dtype},
dtype_dict={"input": dtype},

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Done

f = run_opt_pass(f, relay.transform.InferType())
assert tuple(f.body.checked_type.shape) == ofm_shape


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We should also test invalid dtypes/shapes etc here

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Done

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Should ABS have a rounding mode as implemented in #9514?

Yes, well spotted, I added the rounding_mode attribute :)

ethosu_unary_elementwise operators
"""

def __init__(self, params_class, pattern):
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Suggested change
def __init__(self, params_class, pattern):
def __init__(self, params_class: Type, pattern: CallPattern):

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Done

Comment on lines 90 to 94
activation: str = "NONE",
clip_min: int = 0,
clip_max: int = 0,
ifm_layout: str = "NHWC",
ofm_layout: str = "NHWC",
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@NicolaLancellotti NicolaLancellotti Nov 22, 2021

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Suggested change
activation: str = "NONE",
clip_min: int = 0,
clip_max: int = 0,
ifm_layout: str = "NHWC",
ofm_layout: str = "NHWC",
activation: Optional[str] = "NONE",
clip_min: Optional[int] = 0,
clip_max: Optional[int] = 0,
ifm_layout: Optional[str] = "NHWC",
ofm_layout: Optional[str] = "NHWC",

The docstring says that they are optional.
Actually, we can get the same behaviour with the default values and the None value. Maybe in a future pr we should have only one way to archive that (for the other operators too).

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I added the type hints for the unary elementwise operator, maybe in the follow-up patch we can unify the use for all the operators?

Comment on lines 858 to 861
"""
A class to extract and store parameters of Abs in an NPU friendly way
"""
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The docstring should follow the same convention adopted with the other *Parms classes.

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Done

<< ifm_dtype;

// Assign ofm type
auto ofm_shape = EthosuInferBinaryElementwiseOutputShape(ifm->shape, param->ifm_layout,
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We should rename the function EthosuInferBinaryElementwiseOutputShape if it is used for the unary operators too.

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Done

Comment on lines 18 to 26
import tvm
import tvm.script
from tvm import relay
from tvm.relay.testing import run_opt_pass
from tvm.relay.backend.contrib.ethosu.tir import spec
from tvm.relay.backend.contrib.ethosu.tir.compiler import lower_to_tir
from .infra import make_ethosu_unary_elementwise

import pytest
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Suggested change
import tvm
import tvm.script
from tvm import relay
from tvm.relay.testing import run_opt_pass
from tvm.relay.backend.contrib.ethosu.tir import spec
from tvm.relay.backend.contrib.ethosu.tir.compiler import lower_to_tir
from .infra import make_ethosu_unary_elementwise
import pytest
import pytest
pytest.importorskip("ethosu.vela")
import tvm
import tvm.script
from tvm import relay
from tvm.relay.testing import run_opt_pass
from tvm.relay.backend.contrib.ethosu.tir import spec
from tvm.relay.backend.contrib.ethosu.tir.compiler import lower_to_tir
from .infra import make_ethosu_unary_elementwise

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Done

@NicolaLancellotti
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Should ABS have a rounding mode as implemented in #9514?

Rishabh Jain and others added 2 commits November 22, 2021 13:21
* Added unary elementwise ABS legalization support and tests
* Added unary_elementwise Relay to TIR lowering and tests
* Added TIR to Vela translation and tests
* Added codegen tests

Co-authored-by: Rishabh Jain <[email protected]>
Change-Id: Ic963f1237bdbb493006fbb7e02dc1e5949c7ba46
@ekalda ekalda force-pushed the unary_elementwise_upstream branch from bfdf1f4 to 415826e Compare November 22, 2021 16:10
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LGTM! Thanks, @ekalda.

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@lhutton1 lhutton1 left a comment

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LGTM!

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@manupak manupak left a comment

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LGTM!

@manupak manupak merged commit d061d7f into apache:main Nov 22, 2021
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manupak commented Nov 22, 2021

Thanks all!

@ekalda ekalda deleted the unary_elementwise_upstream branch November 23, 2021 09:25
mehrdadh pushed a commit to mehrdadh/tvm that referenced this pull request Dec 1, 2021
…ache#9530)

* [microNPU] Add unary elementwise operator infrastructure with ABS

* Added unary elementwise ABS legalization support and tests
* Added unary_elementwise Relay to TIR lowering and tests
* Added TIR to Vela translation and tests
* Added codegen tests

Co-authored-by: Rishabh Jain <[email protected]>
mehrdadh pushed a commit to mehrdadh/tvm that referenced this pull request Dec 1, 2021
…ache#9530)

* [microNPU] Add unary elementwise operator infrastructure with ABS

* Added unary elementwise ABS legalization support and tests
* Added unary_elementwise Relay to TIR lowering and tests
* Added TIR to Vela translation and tests
* Added codegen tests

Co-authored-by: Rishabh Jain <[email protected]>
ylc pushed a commit to ylc/tvm that referenced this pull request Jan 7, 2022
…ache#9530)

* [microNPU] Add unary elementwise operator infrastructure with ABS

* Added unary elementwise ABS legalization support and tests
* Added unary_elementwise Relay to TIR lowering and tests
* Added TIR to Vela translation and tests
* Added codegen tests

Co-authored-by: Rishabh Jain <[email protected]>
yangulei pushed a commit to yangulei/tvm that referenced this pull request Jan 11, 2022
…ache#9530)

* [microNPU] Add unary elementwise operator infrastructure with ABS

* Added unary elementwise ABS legalization support and tests
* Added unary_elementwise Relay to TIR lowering and tests
* Added TIR to Vela translation and tests
* Added codegen tests

Co-authored-by: Rishabh Jain <[email protected]>
ylc pushed a commit to ylc/tvm that referenced this pull request Jan 13, 2022
…ache#9530)

* [microNPU] Add unary elementwise operator infrastructure with ABS

* Added unary elementwise ABS legalization support and tests
* Added unary_elementwise Relay to TIR lowering and tests
* Added TIR to Vela translation and tests
* Added codegen tests

Co-authored-by: Rishabh Jain <[email protected]>
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4 participants