support 2 core boot linux but many details need to be modified

crates/arm_gic/src/gic_v2.rs

@@ -254,7 +254,6 @@ impl GicDistributor {
         }
         let reg = vector / 32;
         let mask = 1 << (vector % 32);
-
         if enable {
             self.regs().ISENABLER[reg].set(mask);
         } else {
@@ -263,12 +262,27 @@ impl GicDistributor {
     }
 
     /// Set SGIR for sgi int id and target cpu.
+    /* 
     pub fn set_sgi(&self, cpu_interface: usize, sgi_num: usize) {
         debug!("set sgi!!!!");
         let int_id = (sgi_num & 0b1111) as u32;
         let cpu_targetlist = 1 << (16 + cpu_interface);
         self.regs().SGIR.set(cpu_targetlist | int_id);
     }
+    
+
+    pub fn send_sgi(&mut self, cpu_if: usize, sgi_num: usize) {
+        debug!("send ipi to cpu {}", cpu_if);
+        self.regs().SGIR.set(((1 << (16 + cpu_if)) | (sgi_num & 0b1111)) as u32);
+    }
+    */
+    pub fn send_sgi(&mut self, cpu_if: usize, sgi_num: usize) {
+        debug!("send sgi {} with priority {:#x} to cpu {}", sgi_num, self.get_priority(sgi_num), cpu_if);
+        // debug!("send sgi 2 with priority {:#x} to cpu {}", self.get_priority(2), cpu_if);
+        let sgir = ((1 << (16 + cpu_if)) | (sgi_num & 0b1111)) as u32;
+        debug!("this is sgir value: {:#x}", sgir);
+        self.regs().SGIR.set(sgir);
+    }
 
     /// Get interrupt priority.
     pub fn get_priority(&self, int_id: usize) -> usize {
@@ -278,7 +292,7 @@ impl GicDistributor {
     }
 
     /// Set interrupt priority.
-    pub fn set_priority(&self, int_id: usize, priority: u8) {
+    pub fn set_priority(&mut self, int_id: usize, priority: u8) {
         let idx = (int_id * 8) / 32;
         let offset = (int_id * 8) % 32;
         let mask: u32 = 0xff << offset;
@@ -297,17 +311,15 @@ impl GicDistributor {
     }
 
     /// Set interrupt target cpu.
-    pub fn set_target_cpu(&self, int_id: usize, target: u8) {
+    pub fn set_target_cpu(&mut self, int_id: usize, target: u8) {
         let idx = (int_id * 8) / 32;
         let offset = (int_id * 8) % 32;
         let mask: u32 = 0xff << offset;
 
         let prev_reg_val = self.regs().ITARGETSR[idx].get();
-        // clear target int_id priority and set its priority.
-        let reg_val = (prev_reg_val & !mask) | (((target as u32) << offset) & mask);
-        // println!("idx {}, val {:x}", idx, value);
+        // clear target int_id target and set its target.
+        let reg_val: u32 = (prev_reg_val & !mask) | (((target as u32) << offset) & mask);
         self.regs().ITARGETSR[idx].set(reg_val);
-
     }
 
     /// Set interrupt state to pending or not.

modules/axhal/linker.lds.S

@@ -8,11 +8,11 @@ SECTIONS
     . = BASE_ADDRESS;
     skernel = .;
 
-    .text : ALIGN(4K) {
+    .text : ALIGN(%ALIGN%) {
         stext = .;
         *(.text.boot)
         *(.text .text.*)
-        . = ALIGN(4K);
+        . = ALIGN(%ALIGN%);
         etext = .;
     }
 

modules/axhal/src/arch/aarch64/hv/guest_psci.rs

@@ -73,54 +73,13 @@ fn psci_guest_cpu_on(mpidr: usize, entry: usize, ctx: usize) -> usize {
         warn!("psci_guest_cpu_on: fail to send msg");
         return usize::MAX - 1;
     }
-    0
-}
-
-pub fn psci_ipi_handler(msg: IpiMessage) {
     /* 
-    match msg.ipi_message {
-        IpiInnerMsg::Power(power_msg) => {
-            let trgt_vcpu = match current_cpu().vcpu_array.pop_vcpu_through_vmid(power_msg.src) {
-                None => {
-                    warn!(
-                        "Core {} failed to find target vcpu, source vmid {}",
-                        current_cpu().id,
-                        power_msg.src
-                    );
-                    return;
-                }
-                Some(vcpu) => vcpu,
-            };
-            match power_msg.event {
-                PowerEvent::PsciIpiCpuOn => {
-                    /* 
-                    if trgt_vcpu.state() != VcpuState::Inv {
-                        warn!(
-                            "psci_ipi_handler: target VCPU {} in VM {} is already running",
-                            trgt_vcpu.id(),
-                            trgt_vcpu.vm().unwrap().id()
-                        );
-                        return;
-                    }
-                    info!(
-                        "Core {} (vm {}, vcpu {}) is woke up",
-                        current_cpu().id,
-                        trgt_vcpu.vm().unwrap().id(),
-                        trgt_vcpu.id()
-                    );*/
-                    psci_vcpu_on(trgt_vcpu, power_msg.entry, power_msg.context);
-                }
-                PowerEvent::PsciIpiCpuOff => {
-                    warn!("PowerEvent::PsciIpiCpuOff")
-                }
-            }
-        }
-        _ => {
-            error!("psci_ipi_handler: receive illegal psci ipi type");
-        }
-    }*/
+    let ipi_handler_list = IPI_HANDLER_LIST.lock();
+    debug!("[psci_guest_cpu_on] after ipi_send_msg handler: {:#?}", ipi_handler_list[0].handler as *const());
+    drop(ipi_handler_list);
+    */
+    0
 }
-
 #[inline(never)]
 pub fn smc_call(x0: u32, x1: usize, x2: usize, x3: usize) -> (usize, usize, usize, usize) {
     #[cfg(target_arch = "aarch64")]

modules/axhal/src/arch/aarch64/hv/ipi.rs

@@ -33,7 +33,7 @@ pub struct IpiMessage {
 
 #[derive(Copy, Clone, Debug)]
 pub enum IpiType {
-    Power = 1,
+    Power = 0,
 }
 
 #[derive(Clone, Debug)]
@@ -87,7 +87,7 @@ pub fn ipi_register(ipi_type: IpiType, handler: IpiHandlerFunc) -> bool {
             return false;
         }
     }
-
+    
     while (ipi_type as usize) >= ipi_handler_list.len() {
         ipi_handler_list.push(IpiHandler::new(handler, ipi_type));
     }

modules/axhal/src/arch/aarch64/mod.rs

@@ -35,7 +35,6 @@ pub fn irqs_enabled() -> bool {
 /// It must be called with interrupts enabled, otherwise it will never return.
 #[inline]
 pub fn wait_for_irqs() {
-    // debug!("this is wait for irq!!!!!!!!");
     aarch64_cpu::asm::wfi();
 }
 

modules/axhal/src/irq.rs

@@ -39,18 +39,3 @@ pub(crate) fn register_handler_common(irq_num: usize, handler: IrqHandler) -> bo
 pub fn irq_num_exist(irq_num: usize) -> bool {
     IRQ_HANDLER_TABLE.irq_num_exist(irq_num)
 }
-/* 
-#[cfg(all(feature = "hv", target_arch = "aarch64"))]
-static IRQ_HANDLER_TABLE_EL2: HandlerTable<MAX_IRQ_COUNT> = HandlerTable::new();
-
-#[cfg(all(feature = "hv", target_arch = "aarch64"))]
-#[allow(dead_code)]
-pub(crate) fn register_handler_el2(irq_num: usize, handler: IrqHandler) -> bool {
-    if irq_num < MAX_IRQ_COUNT && IRQ_HANDLER_TABLE_EL2.register_handler(irq_num, handler) {
-        set_enable(irq_num, true);
-        return true;
-    }
-    warn!("register handler for IRQ {} failed", irq_num);
-    false
-}
-*/

modules/axhal/src/lib.rs

@@ -45,7 +45,7 @@ mod platform;
 #[cfg(all(target_arch = "aarch64", feature = "hv"))]
 pub use platform::aarch64_common::gic::IPI_IRQ_NUM;
 #[cfg(all(target_arch = "aarch64", feature = "hv"))]
-pub use platform::aarch64_common::gic::gicc_get_current_irq;
+pub use platform::aarch64_common::gic::{gicc_get_current_irq, deactivate_irq};
 
 pub mod arch;
 pub mod cpu;

modules/axhal/src/platform/aarch64_common/gic.rs

@@ -51,15 +51,18 @@ pub static GICH: GicHypervisorInterface = GicHypervisorInterface::new(phys_to_vi
 
 /// Enables or disables the given IRQ.
 pub fn set_enable(irq_num: usize, enabled: bool) {
-    #[cfg(not(feature = "hv"))]
+    debug!("in platform gic set_enable: irq_num {}, enabled {}", irq_num, enabled);
+    // #[cfg(not(feature = "hv"))]
     GICD.lock().set_enable(irq_num as _, enabled);
+    /* 
     #[cfg(feature = "hv")]
     {
         debug!("in platform gic set_enable: irq_num {}, enabled {}", irq_num, enabled);
-        GICD.lock().set_priority(irq_num as _, 0x7f);
-        GICD.lock().set_target_cpu(irq_num as _, 1 << 0);   // only enable one cpu
+        // GICD.lock().set_priority(irq_num as _, 0x7f);
+        // GICD.lock().set_target_cpu(irq_num as _, 1 << 0);   // only enable one cpu
         GICD.lock().set_enable(irq_num as _, enabled);
     }
+    */
 }
 
 /// Registers an IRQ handler for the given IRQ.
@@ -108,6 +111,7 @@ pub(crate) fn init_secondary() {
 pub fn gicc_get_current_irq() -> (usize, usize) {
     let iar = GICC.get_iar();
     let irq = iar as usize;
+    debug!("this is iar:{:#x}", iar);
     // current_cpu().current_irq = irq;
     let irq = bit_extract(irq, 0, 10);
     let src = bit_extract(irq, 10, 3);
@@ -119,7 +123,7 @@ pub fn gicc_get_current_irq() -> (usize, usize) {
 pub fn interrupt_cpu_ipi_send(cpu_id: usize, ipi_id: usize) {
     debug!("interrupt_cpu_ipi_send: cpu_id {}, ipi_id {}", cpu_id, ipi_id);
     if ipi_id < GIC_SGIS_NUM {
-        GICD.lock().set_sgi(cpu_id, ipi_id);
+       GICD.lock().send_sgi(cpu_id, ipi_id);
     }
 }
 

modules/axhal/src/trap.rs

@@ -28,7 +28,7 @@ pub(crate) fn handle_irq_extern(irq_num: usize) {
 /// Call the external IRQ handler.
 #[allow(dead_code)]
 #[cfg(all(feature = "hv", target_arch = "aarch64"))]
-pub(crate) fn handle_irq_extern_hv(irq_num: usize, src: usize) {
+pub fn handle_irq_extern_hv(irq_num: usize, src: usize) {
     debug!("in handle_irq_extern_hv: irq_num {}, src {}", irq_num, src);
     call_interface!(TrapHandler::handle_irq_hv, irq_num, src);
 }

modules/axruntime/src/hv/aarch64_kernel/guest_psci.rs

@@ -5,6 +5,7 @@ use super::vm_array::{init_vm_vcpu, run_vm_vcpu};
 use crate::hv::HyperCraftHalImpl;
 
 pub(crate) fn psci_ipi_handler(msg: &IpiMessage) {
+    debug!("enter psci_ipi_handler");
     match &msg.ipi_message {
         IpiInnerMsg::Power(power_msg) => {
             // only one vcpu for a pcpu and only one vm. need to modify in the future

modules/axruntime/src/hv/aarch64_kernel/interrupt.rs

@@ -37,32 +37,4 @@ pub fn handle_virtual_interrupt(irq_num: usize, src: usize) {
         current_cpu().cpu_id,
         irq_num
     );
-}
-
-pub fn ipi_irq_handler() {
-    debug!("ipi handler");
-
-    let cpu_id = current_cpu().cpu_id;
-    let mut cpu_if_list = CPU_INT_LIST.lock();
-    let mut msg: Option<IpiMessage> = cpu_if_list[cpu_id].pop();
-    drop(cpu_if_list);
-
-    while !msg.is_none() {
-        let ipi_msg = msg.unwrap();
-        let ipi_type = ipi_msg.ipi_type as usize;
-
-        let ipi_handler_list = IPI_HANDLER_LIST.lock();
-        let len = ipi_handler_list.len();
-        let handler = ipi_handler_list[ipi_type].handler.clone();
-        drop(ipi_handler_list);
-
-        if len <= ipi_type {
-            debug!("illegal ipi type {}", ipi_type)
-        } else {
-            // debug!("ipi type is {:#?}", ipi_msg.ipi_type);
-            handler(&ipi_msg);
-        }
-        let mut cpu_if_list = CPU_INT_LIST.lock();
-        msg = cpu_if_list[cpu_id].pop();
-    }
 }

modules/axruntime/src/hv/aarch64_kernel/ipi_handler.rs

@@ -27,7 +27,7 @@ pub fn ipi_irq_handler() {
         if len <= ipi_type {
             debug!("illegal ipi type {}", ipi_type)
         } else {
-            // debug!("ipi type is {:#?}", ipi_msg.ipi_type);
+            debug!("!!!!!!!!! this is handler: {:#?}", handler as *const());
             handler(&ipi_msg);
         }
         let mut cpu_int_list = CPU_INT_LIST.lock();

modules/axruntime/src/mp.rs

@@ -2,7 +2,7 @@ use axconfig::{SMP, TASK_STACK_SIZE};
 use axhal::mem::{virt_to_phys, VirtAddr};
 use core::sync::atomic::{AtomicUsize, Ordering};
 
-use axhal::gicc_get_current_irq;
+use axhal::{gicc_get_current_irq, deactivate_irq};
 
 use aarch64_cpu::{asm, asm::barrier, registers::*};
 use tock_registers::interfaces::{ReadWriteable, Readable, Writeable};
@@ -78,10 +78,16 @@ pub extern "C" fn rust_main_secondary(cpu_id: usize) -> ! {
 
     #[cfg(not(feature = "multitask"))]
     loop {
-        // let current_el = CurrentEL.read(CurrentEL::EL);
-        // debug!("Current el:{:?}", current_el);
         axhal::arch::wait_for_irqs();
-        // let (id, src) = gicc_get_current_irq();
+        #[cfg(feature = "hv")]
+        {
+            let (irq, src) = gicc_get_current_irq();
+            debug!("src {} id{}", src, irq);
+            deactivate_irq(irq);
+            debug!("after wfi secondary CPU {} irq id {} src {}", cpu_id, irq, src);
+            debug!("is irq enabled: {}", axhal::arch::irqs_enabled());
+            axhal::trap::handle_irq_extern_hv(irq, cpu_id);
+        }
     }
 }