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[fix] cargo doc error in handler_irq, revert gic_if
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@hky1999
hky1999 committed Nov 19, 2024
1 parent 9422e20 commit f34e70e
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2 changes: 1 addition & 1 deletion modules/axhal/src/irq.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,7 @@ pub(crate) fn register_handler_common(irq_num: usize, handler: IrqHandler) -> bo
false
}

/// Core IRQ handling routine, registered at [`IRQ`],
/// Core IRQ handling routine, registered at `axhal::trap::IRQ`,
/// which dispatches IRQs to registered handlers.
///
/// Note: this function is denoted as public here because it'll be called by the
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274 changes: 137 additions & 137 deletions modules/axhal/src/platform/aarch64_common/gic.rs
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Expand Up @@ -74,140 +74,140 @@ pub(crate) fn init_secondary() {
GICC.init();
}

// #[cfg(feature = "hv")]
// mod gic_if {

// use super::{GICC, GICD};
// use arm_gicv2::GicTrait;
// struct GicIfImpl;

// #[crate_interface::impl_interface]
// impl GicTrait for GicIfImpl {
// /// Sets the enable status of a specific interrupt in the GICD (Distributor).
// ///
// /// # Parameters
// /// - `vector`: The interrupt vector number, identifying the interrupt to be enabled or disabled.
// /// - `enable`: A boolean value indicating whether to enable the interrupt. `true` enables the interrupt, `false` disables it.
// ///
// /// This function locks and accesses the GICD controller, then sets the enable status of the specified interrupt vector based on the `enable` parameter.
// /// It provides a mechanism for controlling whether interrupts can trigger CPU responses, used for interrupt management.
// fn set_enable(vector: usize, enable: bool) {
// GICD.lock().set_enable(vector, enable);
// }

// /// Retrieves the enable status of a specified interrupt vector from the GICD.
// ///
// /// # Parameters
// /// - `vector`: The index of the interrupt vector, used to identify a specific interrupt source.
// ///
// /// # Returns
// /// - `bool`: Indicates whether the specified interrupt vector is enabled. `true` means the interrupt vector is enabled, `false` means it is not enabled.
// fn get_enable(vector: usize) -> bool {
// GICD.lock().get_enable(vector)
// }

// /// Get the type of the GICD register
// ///
// /// This function locks the GICD and calls its internal `get_typer` method to retrieve the type of the GICD register
// ///
// /// # Returns
// /// * `u32` - The type of the GICD register
// fn get_typer() -> u32 {
// GICD.lock().get_typer()
// }

// /// Get the Implementer ID Register (IIDR) of the interrupt controller
// ///
// /// This function locks the GICD (interrupt controller) and calls its `get_iidr` method to retrieve the value of the Implementer ID Register.
// /// This register can be used to identify the specific hardware implementer and version.
// fn get_iidr() -> u32 {
// GICD.lock().get_iidr()
// }

// /// Set the state of an interrupt source
// ///
// /// This function updates the state of a specific interrupt source in the GICD (Interrupt Controller).
// /// It first locks the GICD and then updates the interrupt source state using the provided interrupt ID (`int_id`),
// /// new state value (`state`), and current CPU ID (`current_cpu_id`).
// ///
// /// Parameters:
// /// - `int_id`: The ID of the interrupt source.
// /// - `state`: The new state value for the interrupt source.
// /// - `current_cpu_id`: The ID of the current CPU.
// fn set_state(int_id: usize, state: usize, current_cpu_id: usize) {
// GICD.lock().set_state(int_id, state, current_cpu_id);
// }

// /// Get the state of an interrupt source
// ///
// /// This function retrieves the current state of a specific interrupt source.
// ///
// /// Parameters:
// /// - `int_id`: The ID of the interrupt source.
// ///
// /// Returns:
// /// - The current state value.
// fn get_state(int_id: usize) -> usize {
// GICD.lock().get_state(int_id)
// }

// /// Set the ICFGR (Interrupt Configuration and Control Register)
// ///
// /// This function sets the configuration of a specific interrupt source in the ICFGR.
// ///
// /// Parameters:
// /// - `int_id`: The ID of the interrupt source.
// /// - `cfg`: The new configuration value.
// fn set_icfgr(int_id: usize, cfg: u8) {
// GICD.lock().set_icfgr(int_id, cfg);
// }

// /// Get the target CPU for an interrupt source
// ///
// /// This function retrieves the target CPU for a specific interrupt source.
// ///
// /// Parameters:
// /// - `int_id`: The ID of the interrupt source.
// ///
// /// Returns:
// /// - The target CPU ID.
// fn get_target_cpu(int_id: usize) -> usize {
// GICD.lock().get_target_cpu(int_id)
// }

// /// Set the target CPU for an interrupt source
// ///
// /// This function sets the target CPU for a specific interrupt source.
// ///
// /// Parameters:
// /// - `int_id`: The ID of the interrupt source.
// /// - `target`: The new target CPU value.
// fn set_target_cpu(int_id: usize, target: u8) {
// GICD.lock().set_target_cpu(int_id, target);
// }

// /// Get the priority of an interrupt source
// ///
// /// This function retrieves the priority of a specific interrupt source.
// ///
// /// Parameters:
// /// - `int_id`: The ID of the interrupt source.
// ///
// /// Returns:
// /// - The priority value.
// fn get_priority(int_id: usize) -> usize {
// GICD.lock().get_priority(int_id)
// }

// /// Set the priority of an interrupt source
// ///
// /// This function sets the priority of a specific interrupt source.
// ///
// /// Parameters:
// /// - `int_id`: The ID of the interrupt source.
// /// - `priority`: The new priority value.
// fn set_priority(int_id: usize, priority: u8) {
// GICD.lock().set_priority(int_id, priority);
// }
// }
// }
#[cfg(feature = "hv")]
mod gic_if {

use super::{GICC, GICD};
use arm_gicv2::GicTrait;
struct GicIfImpl;

#[crate_interface::impl_interface]
impl GicTrait for GicIfImpl {
/// Sets the enable status of a specific interrupt in the GICD (Distributor).
///
/// # Parameters
/// - `vector`: The interrupt vector number, identifying the interrupt to be enabled or disabled.
/// - `enable`: A boolean value indicating whether to enable the interrupt. `true` enables the interrupt, `false` disables it.
///
/// This function locks and accesses the GICD controller, then sets the enable status of the specified interrupt vector based on the `enable` parameter.
/// It provides a mechanism for controlling whether interrupts can trigger CPU responses, used for interrupt management.
fn set_enable(vector: usize, enable: bool) {
GICD.lock().set_enable(vector, enable);
}

/// Retrieves the enable status of a specified interrupt vector from the GICD.
///
/// # Parameters
/// - `vector`: The index of the interrupt vector, used to identify a specific interrupt source.
///
/// # Returns
/// - `bool`: Indicates whether the specified interrupt vector is enabled. `true` means the interrupt vector is enabled, `false` means it is not enabled.
fn get_enable(vector: usize) -> bool {
GICD.lock().get_enable(vector)
}

/// Get the type of the GICD register
///
/// This function locks the GICD and calls its internal `get_typer` method to retrieve the type of the GICD register
///
/// # Returns
/// * `u32` - The type of the GICD register
fn get_typer() -> u32 {
GICD.lock().get_typer()
}

/// Get the Implementer ID Register (IIDR) of the interrupt controller
///
/// This function locks the GICD (interrupt controller) and calls its `get_iidr` method to retrieve the value of the Implementer ID Register.
/// This register can be used to identify the specific hardware implementer and version.
fn get_iidr() -> u32 {
GICD.lock().get_iidr()
}

/// Set the state of an interrupt source
///
/// This function updates the state of a specific interrupt source in the GICD (Interrupt Controller).
/// It first locks the GICD and then updates the interrupt source state using the provided interrupt ID (`int_id`),
/// new state value (`state`), and current CPU ID (`current_cpu_id`).
///
/// Parameters:
/// - `int_id`: The ID of the interrupt source.
/// - `state`: The new state value for the interrupt source.
/// - `current_cpu_id`: The ID of the current CPU.
fn set_state(int_id: usize, state: usize, current_cpu_id: usize) {
GICD.lock().set_state(int_id, state, current_cpu_id);
}

/// Get the state of an interrupt source
///
/// This function retrieves the current state of a specific interrupt source.
///
/// Parameters:
/// - `int_id`: The ID of the interrupt source.
///
/// Returns:
/// - The current state value.
fn get_state(int_id: usize) -> usize {
GICD.lock().get_state(int_id)
}

/// Set the ICFGR (Interrupt Configuration and Control Register)
///
/// This function sets the configuration of a specific interrupt source in the ICFGR.
///
/// Parameters:
/// - `int_id`: The ID of the interrupt source.
/// - `cfg`: The new configuration value.
fn set_icfgr(int_id: usize, cfg: u8) {
GICD.lock().set_icfgr(int_id, cfg);
}

/// Get the target CPU for an interrupt source
///
/// This function retrieves the target CPU for a specific interrupt source.
///
/// Parameters:
/// - `int_id`: The ID of the interrupt source.
///
/// Returns:
/// - The target CPU ID.
fn get_target_cpu(int_id: usize) -> usize {
GICD.lock().get_target_cpu(int_id)
}

/// Set the target CPU for an interrupt source
///
/// This function sets the target CPU for a specific interrupt source.
///
/// Parameters:
/// - `int_id`: The ID of the interrupt source.
/// - `target`: The new target CPU value.
fn set_target_cpu(int_id: usize, target: u8) {
GICD.lock().set_target_cpu(int_id, target);
}

/// Get the priority of an interrupt source
///
/// This function retrieves the priority of a specific interrupt source.
///
/// Parameters:
/// - `int_id`: The ID of the interrupt source.
///
/// Returns:
/// - The priority value.
fn get_priority(int_id: usize) -> usize {
GICD.lock().get_priority(int_id)
}

/// Set the priority of an interrupt source
///
/// This function sets the priority of a specific interrupt source.
///
/// Parameters:
/// - `int_id`: The ID of the interrupt source.
/// - `priority`: The new priority value.
fn set_priority(int_id: usize, priority: u8) {
GICD.lock().set_priority(int_id, priority);
}
}
}

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