This work has been supported by grant PID2021-123041OB-I00 funded by MCIN/AEI/10.13039/501100011033 (Spanish Ministry of Science and Innovation) and by “ERDF A way of making Europe” (European Regional Development Fund), and by the CM (Community of Madrid, Spain) under grant S2018/TCS-4423.
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Sample hardware address translator for hybrid cache-SPM systems
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