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I added dont_use : "false"; to the NAND gate in cmos_cells.lib.
Expected ABC to not report any dont_use cells, and netlist to contain 1 NAND + 1 NOT.
Actual behavior
In ABC log it says:
ABC: Library "demo" from "/home/test/tmp/cmos_cells.lib" has 3 cells (2 skipped: 2 seq; 0 tri-state; 0 no func; 1 dont_use). Time = 0.00 sec
and the module is implemented with 1 NOR cell and 2 NOT cells.
The text was updated successfully, but these errors were encountered:
bfg86
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this issue
Feb 2, 2022
Hi,
I reported this in the Yosys repository (3065). The testcase requires Yosys to reproduce, let me know if I should make a testcase for ABC only.
Steps to reproduce the issue
unzip testcase.zip
yosys -s syn.ys
Expected behavior
I added dont_use : "false"; to the NAND gate in cmos_cells.lib.
Expected ABC to not report any dont_use cells, and netlist to contain 1 NAND + 1 NOT.
Actual behavior
In ABC log it says:
ABC: Library "demo" from "/home/test/tmp/cmos_cells.lib" has 3 cells (2 skipped: 2 seq; 0 tri-state; 0 no func; 1 dont_use). Time = 0.00 sec
and the module is implemented with 1 NOR cell and 2 NOT cells.
The text was updated successfully, but these errors were encountered: