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------------------------------------------------------------------------------- | ||
LIN bus traffic | ||
------------------------------------------------------------------------------- | ||
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Synthetically generated LIN bus traffic from a debugging session. | ||
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UART settings on LIN are always 19200/8n1, lsb-first; LIN protocol version: 2. | ||
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Logic analyzer setup | ||
-------------------- | ||
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The logic analyzer used was a DreamSourceLab DSLogic Plus (various samplerates): | ||
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Probe LIN | ||
--------------- | ||
0 LIN-Bus | ||
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single_frame.sr | ||
--------------- | ||
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This shows one valid single LIN frame consisting of a header and a response | ||
of 2 data bytes. | ||
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PID is 0xC1 -> ID: 0x01 Parity: 3 | ||
Data 1: 0x11 | ||
Data 2: 0x11 | ||
Checksum: 0x1C | ||
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lin_burst.sr | ||
------------ | ||
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10 valid LIN frames consisting of a header and a response of 3 data bytes each. | ||
The frames are all sent at the highest possible load UART can handle. | ||
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PID is 0xA3 -> ID: 0x23 Parity: 2 | ||
Data 1: 0x11 | ||
Data 2: 0x22 | ||
Checksum: 0x29 | ||
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lin_malformed.sr | ||
---------------- | ||
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Contains complete and incomplete LIN frames. Sometimes the PID is not sent | ||
after the sync. The goal is testing the correct behaviour of the state machine | ||
on protocol violations. | ||
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lin_malformed2.sr | ||
----------------- | ||
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Same as lin_malformed.sr but more traffic. | ||
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lin_stress.sr | ||
------------- | ||
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Different messages with different lengths and a changing bus load. | ||
No protocol violations. |
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