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Ben Dooks
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May 17, 2019
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TDM Audio | ||
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Logic analyser setup | ||
-------------------- | ||
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The logic analyser used was an Salee Logic 1, running at 50Mhz: | ||
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Probe | ||
3 Bit clock | ||
2 Frame sync | ||
1 Data | ||
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tdm-4ch-16bit-cap1.sr | ||
--------------------- | ||
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4 channels, 16 bits per sample. | ||
Data is set of 0x1100 0x3322 0x5544 0x7766 0x9988 0xbbaa 0xddcc 0xffee | ||
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tdm-8ch-16bit-cap1.sr | ||
--------------------- | ||
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8 channels, 16 bits per sample | ||
Data is byte 0x12 repeated. | ||
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