Well managed file descriptor and mmap-ed memory

dlk/python/dlk/templates/include/de10_nano.h

@@ -24,17 +24,6 @@ namespace de10_nano {
 //
 // TCA
 //
-uint8_t* mapPhysicalMemory(size_t base, size_t size) {
-    int fd = open("/dev/mem", O_RDWR | O_SYNC, 0);
-    if (fd == -1)
-        throw std::system_error(errno, std::generic_category());
-    int rw = PROT_READ | PROT_WRITE;
-    auto* mapped_base = reinterpret_cast<uint8_t*>(mmap(nullptr, size, rw, MAP_SHARED, fd, base));
-    if (mapped_base == MAP_FAILED)
-        throw std::system_error(errno, std::generic_category());
-    return mapped_base;
-}
-
 struct Csr {
     static constexpr uint32_t start = 0;
     static constexpr uint32_t admaInputAddress = 1;
@@ -275,10 +264,8 @@ void RunTCA(unsigned long input_addr, unsigned long output_addr, unsigned long k
 
   unsigned use_threshold = (thresholds_addr != 0) ? 1 : 0;
 
-  static volatile uint32_t* csr = nullptr;
-  if (csr == nullptr) {
-    csr = reinterpret_cast<uint32_t*>(mapPhysicalMemory(HPS_TO_FPGA_LW_BASE, 0xFF));
-  }
+  static SimpleMappedMem csr_mmap(HPS_TO_FPGA_LW_BASE, 0xFF);
+  static volatile uint32_t* csr = reinterpret_cast<uint32_t*>(csr_mmap.get());
     auto tileWidth = 32u;
     auto tileHeight = 32u;
     auto p = calcParameters(in_h, in_w, in_c, tileWidth, tileHeight, out_c, k_h, k_w, input_addr, kernel_addr, thresholds_addr, output_addr, use_threshold == 1);

dlk/python/dlk/templates/include/memdriver.h

@@ -21,11 +21,55 @@ limitations under the License.
 #include <stdint.h>
 #include <fcntl.h>
 #include <unistd.h>
+#include <memory>
+#include <system_error>
+
+class FDManager {
+ public:
+  FDManager() : fd(-1) {}
+  FDManager(int fd) : fd(fd) {}
+  ~FDManager() {
+    if (fd >= 0) {
+      close(fd);
+    }
+  }
+  operator int() const { return fd; }
+ private:
+  int fd;
+};
+
+class SimpleMappedMem {
+ public:
+  SimpleMappedMem(std::size_t base, std::size_t size) : length(0) {
+    FDManager fd(open("/dev/mem", O_RDWR | O_SYNC));
+    if (fd == -1) {
+      return;
+    }
+    int rw = PROT_READ | PROT_WRITE;
+    ptr = mmap(nullptr, size, rw, MAP_SHARED, fd, base);
+    if (ptr == MAP_FAILED) {
+      throw std::system_error(errno, std::generic_category());
+    }
+    length = size;
+  }
+  ~SimpleMappedMem() {
+    if (ptr != MAP_FAILED) {
+      munmap(ptr, length);
+    }
+  }
+  void* get() const { return ptr; }
+ private:
+  void* ptr;
+  std::size_t length;
+};
 
 class MappedMem
 {
 public:
   using memtype = volatile void;
+  MappedMem() = delete;
+  MappedMem(const MappedMem &) = delete;
+  MappedMem& operator=(const MappedMem &) = delete;
 
   MappedMem(unsigned long g_paddr,
             uint32_t g_count,
@@ -42,9 +86,10 @@ class MappedMem
     aligned_size = g_paddr - aligned_paddr + (g_count * g_size);
     aligned_size = (aligned_size + 4096 - 1) & ~(4096 - 1);
 
-    int fd = -1;
-    if ((fd = open("/dev/mem", O_RDWR, 0)) < 0)
+    FDManager fd(open("/dev/mem", O_RDWR));
+    if (fd == -1) {
       return;
+    }
 
     aligned_vaddr = mmap(nullptr,
                          aligned_size,
@@ -58,7 +103,6 @@ class MappedMem
     }
 
     mem = (memtype *)((uint32_t)aligned_vaddr + (uint32_t)(g_paddr - aligned_paddr));
-    close(fd);
   }
 
   ~MappedMem()
@@ -132,12 +176,6 @@ class MappedMem
     return mem;
   }
 
-
-private:
-  MappedMem();
-  MappedMem(const MappedMem &);
-  MappedMem& operator=(const MappedMem &);
-
 private:
   memtype *mem;
   uint32_t aligned_size;

dlk/python/dlk/templates/src/network.tpl.cpp

@@ -63,27 +63,9 @@ limitations under the License.
 #include "operators.h"
 
 #ifdef RUN_ON_FPGA
-#include <sys/mman.h>
-#include <cstdint>
-#include <fcntl.h>
-#include <unistd.h>
+#include "memdriver.h"
 #endif
 
-namespace {
-
-uint8_t* mapPhysicalMemory(size_t base, size_t size) {
-    int fd = open("/dev/mem", O_RDWR | O_SYNC, 0);
-    if (fd == -1)
-        throw std::system_error(errno, std::generic_category());
-    int rw = PROT_READ | PROT_WRITE;
-    auto* mapped_base = reinterpret_cast<uint8_t*>(mmap(nullptr, size, rw, MAP_SHARED, fd, base));
-    if (mapped_base == MAP_FAILED)
-        throw std::system_error(errno, std::generic_category());
-    return mapped_base;
-}
-
-} // namespace
-
 {% if config.debug -%}
 #include "c2numpy.h"
 
@@ -259,13 +241,15 @@ bool Network::init()
   {{ '\n' -}}
 
 #if defined RUN_ON_FPGA
-  auto* kernel_buffer = mapPhysicalMemory(KERNEL_ADDR, total_kernel_size);
+  SimpleMappedMem kernel_mmap(KERNEL_ADDR, total_kernel_size);
+  auto kernel_buffer = reinterpret_cast<uint8_t*>(kernel_mmap.get());
   {% for qconv in graph.convs(quantized_only=True) -%}
   {%    set kernel = qconv.input_nodes[1] -%}
   std::memcpy(kernel_buffer + {{qconv.name}}_kernel_offset, {{kernel.name}}.data(), {{qconv.name}}_kernel_size);
   {% endfor -%}
 
-  auto* thresholds_buffer = mapPhysicalMemory(THRESHOLD_ADDR, total_thresholds_size);
+  SimpleMappedMem thresholds_mmap(THRESHOLD_ADDR, total_thresholds_size);
+  auto thresholds_buffer = reinterpret_cast<uint8_t*>(thresholds_mmap.get());
   {% for qconv in graph.convs(quantized_only=True) -%}
       {% if qconv.has_thresholds -%}
           {% set thresholds = qconv.thresholds -%}