Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

s390x: Enable object backend #4680

Merged
merged 1 commit into from
Aug 10, 2022
Merged

s390x: Enable object backend #4680

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
3 changes: 3 additions & 0 deletions cranelift/codegen/src/binemit/mod.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -43,6 +43,8 @@ pub enum Reloc {
Arm64Call,
/// s390x PC-relative 4-byte offset
S390xPCRel32Dbl,
/// s390x PC-relative 4-byte offset to PLT
S390xPLTRel32Dbl,

/// Elf x86_64 32 bit signed PC relative offset to two GOT entries for GD symbol.
ElfX86_64TlsGd,
Expand Down Expand Up @@ -74,6 +76,7 @@ impl fmt::Display for Reloc {
Self::Abs4 => write!(f, "Abs4"),
Self::Abs8 => write!(f, "Abs8"),
Self::S390xPCRel32Dbl => write!(f, "PCRel32Dbl"),
Self::S390xPLTRel32Dbl => write!(f, "PLTRel32Dbl"),
Self::X86PCRel4 => write!(f, "PCRel4"),
Self::X86CallPCRel4 => write!(f, "CallPCRel4"),
Self::X86CallPLTRel4 => write!(f, "CallPLTRel4"),
Expand Down
2 changes: 1 addition & 1 deletion cranelift/codegen/src/isa/s390x/inst/emit.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3216,7 +3216,7 @@ impl MachInstEmit for Inst {
}

let opcode = 0xc05; // BRASL
let reloc = Reloc::S390xPCRel32Dbl;
let reloc = Reloc::S390xPLTRel32Dbl;
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I think this should check is_colocated and use PCRel if true. That is faster than going through the PLT.

Copy link
Member Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

That's not really necessary; the JIT backend doesn't use PLTs anyway, and when generating object files, the linker will omit PLTs when they are not needed. LLVM also always emits PLT relocations and relies on the linker to optimize them away.

if let Some(s) = state.take_stack_map() {
sink.add_stack_map(StackMapExtent::UpcomingBytes(6), s);
}
Expand Down
1 change: 1 addition & 0 deletions cranelift/codegen/src/isa/s390x/inst/mod.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3077,6 +3077,7 @@ impl MachInstLabelUse for LabelUse {
fn from_reloc(reloc: Reloc, addend: Addend) -> Option<Self> {
match (reloc, addend) {
(Reloc::S390xPCRel32Dbl, 2) => Some(LabelUse::PCRel32Dbl),
(Reloc::S390xPLTRel32Dbl, 2) => Some(LabelUse::PCRel32Dbl),
_ => None,
}
}
Expand Down
2 changes: 1 addition & 1 deletion cranelift/jit/src/compiled_blob.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -72,7 +72,7 @@ impl CompiledBlob {
write_unaligned(at as *mut i32, pcrel)
};
}
Reloc::S390xPCRel32Dbl => {
Reloc::S390xPCRel32Dbl | Reloc::S390xPLTRel32Dbl => {
let base = get_address(name);
let what = unsafe { base.offset(isize::try_from(addend).unwrap()) };
let pcrel = i32::try_from(((what as isize) - (at as isize)) >> 1).unwrap();
Expand Down
31 changes: 31 additions & 0 deletions cranelift/object/src/backend.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -73,6 +73,7 @@ impl ObjectBuilder {
target_lexicon::Architecture::X86_64 => object::Architecture::X86_64,
target_lexicon::Architecture::Arm(_) => object::Architecture::Arm,
target_lexicon::Architecture::Aarch64(_) => object::Architecture::Aarch64,
target_lexicon::Architecture::S390x => object::Architecture::S390x,
architecture => {
return Err(ModuleError::Backend(anyhow!(
"target architecture {:?} is unsupported",
Expand Down Expand Up @@ -647,6 +648,36 @@ impl ObjectModule {
12,
)
}
Reloc::S390xPCRel32Dbl => (RelocationKind::Relative, RelocationEncoding::S390xDbl, 32),
Reloc::S390xPLTRel32Dbl => (
RelocationKind::PltRelative,
RelocationEncoding::S390xDbl,
32,
),
Reloc::S390xTlsGd64 => {
assert_eq!(
self.object.format(),
object::BinaryFormat::Elf,
"S390xTlsGd64 is not supported for this file format"
);
(
RelocationKind::Elf(object::elf::R_390_TLS_GD64),
RelocationEncoding::Generic,
64,
)
}
Reloc::S390xTlsGdCall => {
assert_eq!(
self.object.format(),
object::BinaryFormat::Elf,
"S390xTlsGdCall is not supported for this file format"
);
(
RelocationKind::Elf(object::elf::R_390_TLS_GDCALL),
RelocationEncoding::Generic,
0,
)
}
// FIXME
reloc => unimplemented!("{:?}", reloc),
};
Expand Down