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The fully-connected layer for an Image Processing ASIC.

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bytesiz3d/DCNN-Accelerator-FC

 
 

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DCNN-Accelerator

VLSI (CMP305) course project - Spring 2021.

Project Description

  • As part of a larger ASIC chip, this implements the fully-connected layer of a Convolutional Neural Network which processes images and classifies written digits in them.
  • After convolution and pooling layers are applied (locally & high-level analysis), the fully-connected network is applied to globally analyze the whole image, using features extracted from the CNN layers.
  • Fully-connected layers are applied by matrix multiplication of the last CNN layer output & adding a bias. Finally a softmax layer chooses the most probable label for the image.
  • We have also synthesized and routed two submodules, both of which passed the testbenches written for their respective HDL files.

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The fully-connected layer for an Image Processing ASIC.

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