uart16550.core

CAPI=1
[main]
name = ::uart16550:1.5.5
description = UART 16550 transceiver

[fileset rtl]
files =
 rtl/verilog/uart_defines.v[is_include_file]
 rtl/verilog/raminfr.v
 rtl/verilog/uart_receiver.v
 rtl/verilog/uart_regs.v
 rtl/verilog/uart_rfifo.v
 rtl/verilog/uart_sync_flops.v
 rtl/verilog/uart_tfifo.v
 rtl/verilog/uart_top.v
 rtl/verilog/uart_transmitter.v
 rtl/verilog/uart_wb.v
file_type = verilogSource