GitHub - calebofearth/uart16550: UART 16550 core

Name		Name	Last commit message	Last commit date
Latest commit History 113 Commits
bench		bench
doc		doc
fv		fv
lint		lint
rtl		rtl
sim		sim
syn		syn
uart16550.core		uart16550.core

About

UART 16550 core

Report repository

Releases

No releases published

Packages

No packages published

Languages

Verilog 100.0%