Resolve backport conflicts

src/test/scala/chiselTests/ClockSpec.scala

@@ -34,52 +34,6 @@ class ClockSpec extends ChiselPropSpec {
     circuit.contains("reg a : UInt<1>, clock2") should be(true)
   }
 
-  property("Should be able to override the value of the implicit clock") {
-    val verilog = ChiselStage.emitSystemVerilog(new Module {
-      val gate = IO(Input(Bool()))
-      val in = IO(Input(UInt(8.W)))
-      val out = IO(Output(UInt(8.W)))
-      val gatedClock = (clock.asBool || gate).asClock
-      override protected def implicitClock = gatedClock
-
-      val r = Reg(UInt(8.W))
-      out := r
-      r := in
-    })
-    verilog should include("gatedClock = clock | gate;")
-    verilog should include("always @(posedge gatedClock)")
-  }
-
-  property("Should be able to add an implicit clock to a RawModule") {
-    val verilog = ChiselStage.emitSystemVerilog(new RawModule with ImplicitClock {
-      val foo = IO(Input(Bool()))
-      val in = IO(Input(UInt(8.W)))
-      val out = IO(Output(UInt(8.W)))
-      override protected val implicitClock = (!foo).asClock
-
-      val r = Reg(UInt(8.W))
-      out := r
-      r := in
-    })
-    verilog should include("always @(posedge implicitClock)")
-  }
-
-  property("Chisel should give a decent error message if you try to use a clock before defining it") {
-    val e = the[ChiselException] thrownBy (
-      ChiselStage.emitCHIRRTL(
-        new RawModule with ImplicitClock {
-          val r = Reg(UInt(8.W))
-          val foo = IO(Input(Clock()))
-          override protected def implicitClock = foo
-        },
-        args = Array("--throw-on-first-error")
-      )
-    )
-    e.getMessage should include(
-      "The implicit clock is null which means the code that sets its definition has not yet executed."
-    )
-  }
-
   property("Chisel should give a decent error message if you use an unbound Clock") {
     val e = the[ChiselException] thrownBy (
       ChiselStage.emitCHIRRTL(