Merge branch 'master' into release

chipsalliance · Sep 14, 2017 · d717ddc · d717ddc
2 parents a5e07f4 + 6a57642
commit d717ddc
Show file tree

Hide file tree

Showing 44 changed files with 506 additions and 255 deletions.
diff --git a/Makefile b/Makefile
@@ -25,15 +25,15 @@ c_resources_dir := src/main/resources
 
 test_outs    := $(addprefix $(targetDir)/, $(addsuffix .out, $(test_results)))
 
-.PHONY:	smoke publish-local check clean jenkins-build coverage scaladoc test checkstyle compile
+.PHONY:	smoke publish-local pubishLocal check clean jenkins-build coverage scaladoc test checkstyle compile
 
-default:	publish-local
+default:	publishLocal
 
 smoke compile:
 	$(SBT) $(SBT_FLAGS) compile
 
-publish-local:
-	$(SBT) $(SBT_FLAGS) publish-local
+publish-local publishLocal:
+	$(SBT) $(SBT_FLAGS) publishLocal
 
 test:
 	$(SBT) $(SBT_FLAGS) test
@@ -69,7 +69,7 @@ site:
 # We need to run the coverage tests last, since Jenkins will fail the build if it can't find their results.
 jenkins-build: clean
 	$(SBT) $(SBT_FLAGS) test
-	$(SBT) $(SBT_FLAGS) clean publish-local
+	$(SBT) $(SBT_FLAGS) clean publishLocal
 	$(SBT) $(SBT_FLAGS) scalastyle coverage test
 	$(SBT) $(SBT_FLAGS) coverageReport
 
@@ -87,3 +87,8 @@ $(targetDir)/%.h:	$(c_resources_dir)/%.h
 
 $(targetDir)/%.out:	$(targetDir)/%
 	$(SBT) $(SBT_FLAGS) "test:runMain ChiselTests.MiniChisel $(notdir $(basename $<)) $(CHISEL_FLAGS) --test --targetDir $(targetDir)"
+
+# The "last-resort" rule.
+# We assume the target is something like "+clean".
+%::
+	$(SBT) $(SBT_FLAGS) $@
diff --git a/README.md b/README.md
@@ -1,6 +1,10 @@
 # Chisel3
-Chisel3 is a new Firrtl based chisel.
-It is currently in BETA VERSION, so some Chisel features may change in the coming months.
+
+Chisel is a new hardware construction language to support advanced hardware design and circuit generation.
+The latest version of [Chisel](https://chisel.eecs.berkeley.edu/) is Chisel3,
+which uses Firrtl as an intermediate hardware representation language.
+
+Chisel3 is currently in BETA VERSION, so some Chisel features may change in the coming months.
 
 Please visit the [Wiki](https://github.com/ucb-bar/chisel3/wiki) for a more
 detailed description.

diff --git a/build.sbt b/build.sbt
@@ -1,29 +1,47 @@
 // See LICENSE for license details.
 
-site.settings
-
-site.includeScaladoc()
-
-ghpages.settings
-
-import UnidocKeys._
-
-lazy val customUnidocSettings = unidocSettings ++ Seq (
-  doc in Compile := (doc in ScalaUnidoc).value,
-  target in unidoc in ScalaUnidoc := crossTarget.value / "api"
-)
+enablePlugins(SiteScaladocPlugin)
+
+enablePlugins(GhpagesPlugin)
+
+def scalacOptionsVersion(scalaVersion: String): Seq[String] = {
+  Seq() ++ {
+    // If we're building with Scala > 2.11, enable the compile option
+    //  switch to support our anonymous Bundle definitions:
+    //  https://github.com/scala/bug/issues/10047
+    CrossVersion.partialVersion(scalaVersion) match {
+      case Some((2, scalaMajor: Int)) if scalaMajor < 12 => Seq()
+      case _ => Seq("-Xsource:2.11")
+    }
+  }
+}
+
+def javacOptionsVersion(scalaVersion: String): Seq[String] = {
+  Seq() ++ {
+    // Scala 2.12 requires Java 8. We continue to generate
+    //  Java 7 compatible code for Scala 2.11
+    //  for compatibility with old clients.
+    CrossVersion.partialVersion(scalaVersion) match {
+      case Some((2, scalaMajor: Int)) if scalaMajor < 12 =>
+        Seq("-source", "1.7", "-target", "1.7")
+      case _ =>
+        Seq("-source", "1.8", "-target", "1.8")
+    }
+  }
+}
 
 lazy val commonSettings = Seq (
   organization := "edu.berkeley.cs",
-  version := "3.0-SNAPSHOT_2017-08-16",
-  git.remoteRepo := "[email protected]:ucb-bar/chisel3.git",
+  version := "3.0-SNAPSHOT_2017-09-14",
+  git.remoteRepo := "[email protected]:freechipsproject/chisel3.git",
   autoAPIMappings := true,
   scalaVersion := "2.11.11",
+  crossScalaVersions := Seq("2.11.11", "2.12.3"),
   resolvers ++= Seq(
     Resolver.sonatypeRepo("snapshots"),
     Resolver.sonatypeRepo("releases")
   ),
-  scalacOptions := Seq("-deprecation", "-feature"),
+  scalacOptions := Seq("-deprecation", "-feature") ++ scalacOptionsVersion(scalaVersion.value),
   libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value,
   addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full),
   // Use the root project's unmanaged base for all sub-projects.
@@ -54,8 +72,8 @@ lazy val publishSettings = Seq (
       </license>
     </licenses>
     <scm>
-      <url>https://github.com/ucb-bar/chisel3.git</url>
-      <connection>scm:git:github.com/ucb-bar/chisel3.git</connection>
+      <url>https://github.com/freechipsproject/chisel3.git</url>
+      <connection>scm:git:github.com/freechipsproject/chisel3.git</connection>
     </scm>
     <developers>
       <developer>
@@ -77,7 +95,7 @@ lazy val publishSettings = Seq (
   }
 )
 
-val defaultVersions = Map("firrtl" -> "1.0-SNAPSHOT_2017-08-16")
+val defaultVersions = Map("firrtl" -> "1.0-SNAPSHOT_2017-09-14")
 
 lazy val chiselSettings = Seq (
   name := "chisel3",
@@ -89,13 +107,13 @@ lazy val chiselSettings = Seq (
   libraryDependencies ++= Seq(
     "org.scalatest" %% "scalatest" % "3.0.1" % "test",
     "org.scalacheck" %% "scalacheck" % "1.13.4" % "test",
-    "com.github.scopt" %% "scopt" % "3.5.0"
+    "com.github.scopt" %% "scopt" % "3.6.0"
   ),
 
   // Tests from other projects may still run concurrently.
   parallelExecution in Test := true,
 
-  javacOptions ++= Seq("-target", "1.7")
+  javacOptions ++= javacOptionsVersion(scalaVersion.value)
 )
 
 lazy val coreMacros = (project in file("coreMacros")).
@@ -112,14 +130,14 @@ lazy val root = RootProject(file("."))
 
 lazy val chisel = (project in file(".")).
   enablePlugins(BuildInfoPlugin).
+  enablePlugins(ScalaUnidocPlugin).
   settings(
     buildInfoPackage := name.value,
     buildInfoOptions += BuildInfoOption.BuildTime,
     buildInfoUsePackageAsPath := true,
     buildInfoKeys := Seq[BuildInfoKey](buildInfoPackage, version, scalaVersion, sbtVersion)
   ).
   settings(commonSettings: _*).
-  settings(customUnidocSettings: _*).
   settings(chiselSettings: _*).
   settings(publishSettings: _*).
   // Prevent separate JARs from being generated for coreMacros and chiselFrontend.

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -76,104 +76,26 @@ sealed abstract class Aggregate extends Data {
   private[core] override def connectFromBits(that: Bits)(implicit sourceInfo: SourceInfo,
       compileOptions: CompileOptions): Unit = {
     var i = 0
-    val bits = Wire(UInt(this.width), init=that)  // handles width padding
+    val bits = WireInit(UInt(this.width), that)  // handles width padding
     for (x <- flatten) {
       x.connectFromBits(bits(i + x.getWidth - 1, i))
       i += x.getWidth
     }
   }
 }
 
-object Vec {
+trait VecFactory {
   /** Creates a new [[Vec]] with `n` entries of the specified data type.
     *
     * @note elements are NOT assigned by default and have no value
     */
-  def apply[T <: Data](n: Int, gen: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] = new Vec(gen.chiselCloneType, n)
-
-  @deprecated("Vec argument order should be size, t; this will be removed by the official release", "chisel3")
-  def apply[T <: Data](gen: T, n: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] = new Vec(gen.chiselCloneType, n)
-
-  /** Creates a new [[Vec]] composed of elements of the input Seq of [[Data]]
-    * nodes.
-    *
-    * @note input elements should be of the same type (this is checked at the
-    * FIRRTL level, but not at the Scala / Chisel level)
-    * @note the width of all output elements is the width of the largest input
-    * element
-    * @note output elements are connected from the input elements
-    */
-  def apply[T <: Data](elts: Seq[T]): Vec[T] = macro VecTransform.apply_elts
-
-  def do_apply[T <: Data](elts: Seq[T])(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] = {
-    // REVIEW TODO: this should be removed in favor of the apply(elts: T*)
-    // varargs constructor, which is more in line with the style of the Scala
-    // collection API. However, a deprecation phase isn't possible, since
-    // changing apply(elt0, elts*) to apply(elts*) causes a function collision
-    // with apply(Seq) after type erasure. Workarounds by either introducing a
-    // DummyImplicit or additional type parameter will break some code.
-
-    // Check that types are homogeneous.  Width mismatch for Elements is safe.
-    require(!elts.isEmpty)
-    elts.foreach(requireIsHardware(_, "vec element"))
-
-    val vec = Wire(new Vec(cloneSupertype(elts, "Vec"), elts.length))
-
-    // TODO: try to remove the logic for this mess
-    elts.head.direction match {
-      case ActualDirection.Input | ActualDirection.Output | ActualDirection.Unspecified =>
-        // When internal wires are involved, driver / sink must be specified explicitly, otherwise
-        // the system is unable to infer which is driver / sink
-        (vec zip elts).foreach(x => x._1 := x._2)
-      case ActualDirection.Bidirectional(_) =>
-        // For bidirectional, must issue a bulk connect so subelements are resolved correctly.
-        // Bulk connecting two wires may not succeed because Chisel frontend does not infer
-        // directions.
-        (vec zip elts).foreach(x => x._1 <> x._2)
+  def apply[T <: Data](n: Int, gen: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] = {
+    if (compileOptions.declaredTypeMustBeUnbound) {
+      requireIsChiselType(gen, "vec type")
     }
-    vec
+    new Vec(gen.chiselCloneType, n)
   }
 
-  /** Creates a new [[Vec]] composed of the input [[Data]] nodes.
-    *
-    * @note input elements should be of the same type (this is checked at the
-    * FIRRTL level, but not at the Scala / Chisel level)
-    * @note the width of all output elements is the width of the largest input
-    * element
-    * @note output elements are connected from the input elements
-    */
-  def apply[T <: Data](elt0: T, elts: T*): Vec[T] = macro VecTransform.apply_elt0
-
-  def do_apply[T <: Data](elt0: T, elts: T*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] =
-    apply(elt0 +: elts.toSeq)
-
-  /** Creates a new [[Vec]] of length `n` composed of the results of the given
-    * function applied over a range of integer values starting from 0.
-    *
-    * @param n number of elements in the vector (the function is applied from
-    * 0 to `n-1`)
-    * @param gen function that takes in an Int (the index) and returns a
-    * [[Data]] that becomes the output element
-    */
-  def tabulate[T <: Data](n: Int)(gen: (Int) => T): Vec[T] = macro VecTransform.tabulate
-
-  def do_tabulate[T <: Data](n: Int)(gen: (Int) => T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] =
-    apply((0 until n).map(i => gen(i)))
-
-  /** Creates a new [[Vec]] of length `n` composed of the result of the given
-    * function repeatedly applied.
-    *
-    * @param n number of elements (amd the number of times the function is
-    * called)
-    * @param gen function that generates the [[Data]] that becomes the output
-    * element
-    */
-  @deprecated("Vec.fill(n)(gen) is deprecated. Please use Vec(Seq.fill(n)(gen))", "chisel3")
-  def fill[T <: Data](n: Int)(gen: => T): Vec[T] = macro VecTransform.fill
-
-  def do_fill[T <: Data](n: Int)(gen: => T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] =
-    apply(Seq.fill(n)(gen))
-
   /** Truncate an index to implement modulo-power-of-2 addressing. */
   private[core] def truncateIndex(idx: UInt, n: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = {
     val w = BigInt(n-1).bitLength
@@ -184,6 +106,8 @@ object Vec {
   }
 }
 
+object Vec extends VecFactory
+
 /** A vector (array) of [[Data]] elements. Provides hardware versions of various
   * collection transformation functions found in software array implementations.
   *
@@ -208,7 +132,7 @@ object Vec {
   *  - when multiple conflicting assignments are performed on a Vec element, the last one takes effect (unlike Mem, where the result is undefined)
   *  - Vecs, unlike classes in Scala's collection library, are propagated intact to FIRRTL as a vector type, which may make debugging easier
   */
-sealed class Vec[T <: Data] private (gen: => T, val length: Int)
+sealed class Vec[T <: Data] private[core] (gen: => T, val length: Int)
     extends Aggregate with VecLike[T] {
   private[core] override def typeEquivalent(that: Data): Boolean = that match {
     case that: Vec[T] =>
@@ -326,6 +250,74 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int)
   }
 }
 
+object VecInit {
+  /** Creates a new [[Vec]] composed of elements of the input Seq of [[Data]]
+    * nodes.
+    *
+    * @note input elements should be of the same type (this is checked at the
+    * FIRRTL level, but not at the Scala / Chisel level)
+    * @note the width of all output elements is the width of the largest input
+    * element
+    * @note output elements are connected from the input elements
+    */
+  def apply[T <: Data](elts: Seq[T]): Vec[T] = macro VecTransform.apply_elts
+
+  def do_apply[T <: Data](elts: Seq[T])(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] = {
+    // REVIEW TODO: this should be removed in favor of the apply(elts: T*)
+    // varargs constructor, which is more in line with the style of the Scala
+    // collection API. However, a deprecation phase isn't possible, since
+    // changing apply(elt0, elts*) to apply(elts*) causes a function collision
+    // with apply(Seq) after type erasure. Workarounds by either introducing a
+    // DummyImplicit or additional type parameter will break some code.
+
+    // Check that types are homogeneous.  Width mismatch for Elements is safe.
+    require(!elts.isEmpty)
+    elts.foreach(requireIsHardware(_, "vec element"))
+
+    val vec = Wire(new Vec(cloneSupertype(elts, "Vec"), elts.length))
+
+    // TODO: try to remove the logic for this mess
+    elts.head.direction match {
+      case ActualDirection.Input | ActualDirection.Output | ActualDirection.Unspecified =>
+        // When internal wires are involved, driver / sink must be specified explicitly, otherwise
+        // the system is unable to infer which is driver / sink
+        (vec zip elts).foreach(x => x._1 := x._2)
+      case ActualDirection.Bidirectional(_) =>
+        // For bidirectional, must issue a bulk connect so subelements are resolved correctly.
+        // Bulk connecting two wires may not succeed because Chisel frontend does not infer
+        // directions.
+        (vec zip elts).foreach(x => x._1 <> x._2)
+    }
+    vec
+  }
+
+  /** Creates a new [[Vec]] composed of the input [[Data]] nodes.
+    *
+    * @note input elements should be of the same type (this is checked at the
+    * FIRRTL level, but not at the Scala / Chisel level)
+    * @note the width of all output elements is the width of the largest input
+    * element
+    * @note output elements are connected from the input elements
+    */
+  def apply[T <: Data](elt0: T, elts: T*): Vec[T] = macro VecTransform.apply_elt0
+
+  def do_apply[T <: Data](elt0: T, elts: T*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] =
+    apply(elt0 +: elts.toSeq)
+
+  /** Creates a new [[Vec]] of length `n` composed of the results of the given
+    * function applied over a range of integer values starting from 0.
+    *
+    * @param n number of elements in the vector (the function is applied from
+    * 0 to `n-1`)
+    * @param gen function that takes in an Int (the index) and returns a
+    * [[Data]] that becomes the output element
+    */
+  def tabulate[T <: Data](n: Int)(gen: (Int) => T): Vec[T] = macro VecTransform.tabulate
+
+  def do_tabulate[T <: Data](n: Int)(gen: (Int) => T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] =
+    apply((0 until n).map(i => gen(i)))
+}
+
 /** A trait for [[Vec]]s containing common hardware generators for collection
   * operations.
   */

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Assert.scala b/chiselFrontend/src/main/scala/chisel3/core/Assert.scala
@@ -51,7 +51,7 @@ object assert { // scalastyle:ignore object.name
   }
 
   def apply_impl_do(cond: Bool, line: String, message: Option[String], data: Bits*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions) {
-    when (!(cond || Builder.forcedReset)) {
+    when (!(cond || Module.reset.toBool)) {
       val fmt = message match {
         case Some(str) => s"Assertion failed: $str\n    at $line\n"
         case None => s"Assertion failed\n    at $line\n"
@@ -77,7 +77,7 @@ object assert { // scalastyle:ignore object.name
 object stop { // scalastyle:ignore object.name
   /** Terminate execution with a failure code. */
   def apply(code: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = {
-    when (!Builder.forcedReset) {
+    when (!Module.reset.toBool) {
       pushCommand(Stop(sourceInfo, Node(Builder.forcedClock), code))
     }
   }