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Type of issue: Bug Report
Please provide the steps to reproduce the problem:
mill __.test
What is the current behavior? Verilator compile error while testing, complaining Verilator need a newer compiler above c++ 14.
What is the expected behavior? Test should work properly.
Please tell us about your environment:
6.0
Linux ArchLinux 6.7.4-zen1-1-zen #1 ZEN SMP PREEMPT_DYNAMIC Mon, 05 Feb 2024 22:07:37 +0000 x86_64 GNU/Linux
Verilator 5.021 devel rev v5.020-105-ga187a16e5
oss-cad-suite
Other Information
Error logs of test:
LANG=C mill __.test [83/83] TestProject.test.test GCDSpec: - Gcd should calculate proper greatest common denominator *** FAILED *** java.lang.Exception: make: Entering directory '/tmp/chisel3.simulator.EphemeralSimulator/357569@PeterWang-ArchLinux/workdir-default' ls . | grep -v Makefile | grep -v execution-script.txt | xargs rm -rf \ /opt/oss-cad-suite/bin/verilator \ '--cc' \ '--exe' \ '--build' \ '-o' \ '../simulation' \ '--top-module' \ 'svsimTestbench' \ '--Mdir' \ 'verilated-sources' \ '-CFLAGS' \ '-std=c++11 -I/tmp/chisel3.simulator.EphemeralSimulator/357569@PeterWang-ArchLinux/workdir-default -DSVSIM_ENABLE_VERILATOR_SUPPORT' \ '../primary-sources/DecoupledGcd.sv' 'testbench.sv' '../generated-sources/c-dpi-bridge.cpp' '../generated-sources/simulation-driver.cpp' make[1]: Entering directory '/tmp/chisel3.simulator.EphemeralSimulator/357569@PeterWang-ArchLinux/workdir-default/verilated-sources' g++ -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -std=c++11 -I/tmp/chisel3.simulator.EphemeralSimulator/357569@PeterWang-ArchLinux/workdir-default -DSVSIM_ENABLE_VERILATOR_SUPPORT -Os -c -o c-dpi-bridge.o c-dpi-bridge.cpp g++ -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -std=c++11 -I/tmp/chisel3.simulator.EphemeralSimulator/357569@PeterWang-ArchLinux/workdir-default -DSVSIM_ENABLE_VERILATOR_SUPPORT -Os -c -o simulation-driver.o simulation-driver.cpp In file included from /opt/oss-cad-suite/share/verilator/include/verilated.h:42, from ./VsvsimTestbench.h:11, from simulation-driver.cpp:883: /opt/oss-cad-suite/share/verilator/include/verilatedos.h:265:3: error: #error "Verilator requires a C++14 or newer compiler" 265 | # error "Verilator requires a C++14 or newer compiler" | ^~~~~ /opt/oss-cad-suite/share/verilator/include/verilated.h:76:22: error: 'literals' is not a namespace-name 76 | using namespace std::literals; // "<std::string literal>"s; see SF.7 core guideline | ^~~~~~~~ In file included from /opt/oss-cad-suite/share/verilator/include/verilated.h:950: /opt/oss-cad-suite/share/verilator/include/verilated_types.h: In function 'std::string VL_TO_STRING(const VlEvent&)': /opt/oss-cad-suite/share/verilator/include/verilated_types.h:266:12: error: unable to find string literal operator 'operator""s' with 'const char [11]', 'long unsigned int' arguments 266 | return "triggered="s + (e.isTriggered() ? "true" : "false"); | ^~~~~~~~~~~~~ /opt/oss-cad-suite/share/verilator/include/verilated_types.h: In function 'std::string VL_TO_STRING(const VlEventBase&)': /opt/oss-cad-suite/share/verilator/include/verilated_types.h:277:12: error: unable to find string literal operator 'operator""s' with 'const char [11]', 'long unsigned int' arguments 277 | return "triggered="s + (e.isTriggered() ? "true" : "false"); | ^~~~~~~~~~~~~ /opt/oss-cad-suite/share/verilator/include/verilated_types.h: In constructor 'VlClassRef<T_Class>::VlClassRef(VlClassRef<T_Class>&&)': /opt/oss-cad-suite/share/verilator/include/verilated_types.h:1651:23: error: 'exchange' is not a member of 'std' 1651 | : m_objp{std::exchange(moved.m_objp, nullptr)} {} | ^~~~~~~~ /opt/oss-cad-suite/share/verilator/include/verilated_types.h:1651:23: note: 'std::exchange' is only available from C++14 onwards /opt/oss-cad-suite/share/verilator/include/verilated_types.h: In constructor 'VlClassRef<T_Class>::VlClassRef(VlClassRef<T_OtherClass>&&)': /opt/oss-cad-suite/share/verilator/include/verilated_types.h:1661:23: error: 'exchange' is not a member of 'std' 1661 | : m_objp{std::exchange(moved.m_objp, nullptr)} {} | ^~~~~~~~ /opt/oss-cad-suite/share/verilator/include/verilated_types.h:1661:23: note: 'std::exchange' is only available from C++14 onwards /opt/oss-cad-suite/share/verilator/include/verilated_types.h: In member function 'VlClassRef<T_Class>& VlClassRef<T_Class>::operator=(VlClassRef<T_Class>&&)': /opt/oss-cad-suite/share/verilator/include/verilated_types.h:1676:23: error: 'exchange' is not a member of 'std' 1676 | m_objp = std::exchange(moved.m_objp, nullptr); | ^~~~~~~~ /opt/oss-cad-suite/share/verilator/include/verilated_types.h:1676:23: note: 'std::exchange' is only available from C++14 onwards /opt/oss-cad-suite/share/verilator/include/verilated_types.h: In member function 'VlClassRef<T_Class>& VlClassRef<T_Class>::operator=(VlClassRef<T_OtherClass>&&)': /opt/oss-cad-suite/share/verilator/include/verilated_types.h:1691:23: error: 'exchange' is not a member of 'std' 1691 | m_objp = std::exchange(moved.m_objp, nullptr); | ^~~~~~~~ /opt/oss-cad-suite/share/verilator/include/verilated_types.h:1691:23: note: 'std::exchange' is only available from C++14 onwards make[1]: *** [VsvsimTestbench.mk:65: simulation-driver.o] Error 1 make[1]: Leaving directory '/tmp/chisel3.simulator.EphemeralSimulator/357569@PeterWang-ArchLinux/workdir-default/verilated-sources' %Error: make -C verilated-sources -f VsvsimTestbench.mk -j 1 exited with 2 %Error: Command Failed ulimit -s unlimited 2>/dev/null; exec /opt/oss-cad-suite/share/verilator/bin/verilator_bin --cc --exe --build -o ../simulation --top-module svsimTestbench --Mdir verilated-sources -CFLAGS -std=c++11\ -I/tmp/chisel3.simulator.EphemeralSimulator/357569\@PeterWang-ArchLinux/workdir-default\ -DSVSIM_ENABLE_VERILATOR_SUPPORT ../primary-sources/DecoupledGcd.sv testbench.sv ../generated-sources/c-dpi-bridge.cpp ../generated-sources/simulation-driver.cpp make: *** [Makefile:12: simulation] Error 2 make: Leaving directory '/tmp/chisel3.simulator.EphemeralSimulator/357569@PeterWang-ArchLinux/workdir-default' at svsim.Workspace.compile(Workspace.scala:390) at chisel3.simulator.Simulator$WorkspaceCompiler.liftedTree1$1(Simulator.scala:60) at chisel3.simulator.Simulator$WorkspaceCompiler.process(Simulator.scala:53) at chisel3.simulator.SingleBackendSimulator.processBackends(Simulator.scala:139) at chisel3.simulator.SingleBackendSimulator.processBackends$(Simulator.scala:138) at chisel3.simulator.EphemeralSimulator$DefaultSimulator.processBackends(EphemeralSimulator.scala:27) at chisel3.simulator.Simulator._simulate(Simulator.scala:116) at chisel3.simulator.Simulator._simulate$(Simulator.scala:97) at chisel3.simulator.EphemeralSimulator$DefaultSimulator._simulate(EphemeralSimulator.scala:27) at chisel3.simulator.SingleBackendSimulator.simulate(Simulator.scala:146) ... 1 targets failed TestProject.test.test 1 tests failed: gcd.GCDSpec Gcd should calculate proper greatest common denominator
What is the use case for changing the behavior? Circuit unit test.
The text was updated successfully, but these errors were encountered:
Fixed in #3876.
Sorry, something went wrong.
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Type of issue: Bug Report
Please provide the steps to reproduce the problem:
mill __.test
What is the current behavior?
Verilator compile error while testing, complaining Verilator need a newer compiler above c++ 14.
What is the expected behavior?
Test should work properly.
Please tell us about your environment:
6.0
Linux ArchLinux 6.7.4-zen1-1-zen #1 ZEN SMP PREEMPT_DYNAMIC Mon, 05 Feb 2024 22:07:37 +0000 x86_64 GNU/Linux
Verilator 5.021 devel rev v5.020-105-ga187a16e5
(integrated withoss-cad-suite
)Other Information
Error logs of test:
What is the use case for changing the behavior?
Circuit unit test.
The text was updated successfully, but these errors were encountered: