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Fix tests to avoid inferred width ports on public modules. #3869

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dtzSiFive
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@dtzSiFive dtzSiFive commented Feb 26, 2024

Public modules can't have inferred widths or abstract reset, fix tests to emit spec-compliant FIRRTL 4.0.

Contributor Checklist

  • Did you add Scaladoc to every public function/method?
  • Did you add at least one test demonstrating the PR?
  • Did you delete any extraneous printlns/debugging code?
  • Did you specify the type of improvement?
  • Did you add appropriate documentation in docs/src?
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Type of Improvement

  • API modification

Desired Merge Strategy

  • Squash: The PR will be squashed and merged (choose this if you have no preference).

Release Notes

Main module are "public" (#3813, soon mandatory) which means they cannot have inferred widths or abstract resets. Code relying on old behavior will presently encounter an error in firtool.

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@dtzSiFive
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CI failure re:jextract is due to the usual problem of the URL expiring, and is fixed here: #3868 .

@dtzSiFive dtzSiFive force-pushed the fix/public-ports-known-width-in-tests branch from 2ab2887 to 16fd7fe Compare February 26, 2024 16:02
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@seldridge seldridge left a comment

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LGTM

One questions about if this needs output coercion or not.

src/test/scala/chiselTests/ChiselSpec.scala Outdated Show resolved Hide resolved
@dtzSiFive
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This is marked "API modification" label -- that's so release notes flag it as such, right? Sounds good to me.
I wasn't sure since the PR itself changes nothing but reflects a change made earlier, but if I understand right that makes sense, thanks! I'll update the PR description.

@dtzSiFive dtzSiFive enabled auto-merge (squash) February 26, 2024 17:06
@dtzSiFive dtzSiFive merged commit 9f0881e into chipsalliance:main Feb 26, 2024
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@dtzSiFive dtzSiFive deleted the fix/public-ports-known-width-in-tests branch February 26, 2024 17:17
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3 participants