Add ElaboratedCircuit and deprecate use of internal ir Circuit #4683
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Change ChiselCircuitAnnotation and CircuitSerializationAnnotation to no longer be case classes to help with the transition to ElaboratedCircuit.
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Change ChiselCircuitAnnotation and CircuitSerializationAnnotation to no longer be case classes to help with the transition to ElaboratedCircuit. (cherry picked from commit 4d75573) # Conflicts: # core/src/main/scala/chisel3/experimental/hierarchy/core/Definition.scala # core/src/main/scala/chisel3/internal/Builder.scala # src/main/scala/chisel3/stage/ChiselOptions.scala # src/main/scala/chisel3/stage/phases/AddImplicitOutputAnnotationFile.scala # src/main/scala/chisel3/stage/phases/AddImplicitOutputFile.scala # src/main/scala/chisel3/stage/phases/Convert.scala # src/main/scala/chisel3/stage/phases/Elaborate.scala # src/test/scala/circtTests/stage/ChiselStageSpec.scala
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…ort #4683) (#4693) * Add ElaboratedCircuit and deprecate use of internal ir Circuit (#4683) Change ChiselCircuitAnnotation and CircuitSerializationAnnotation to no longer be case classes to help with the transition to ElaboratedCircuit. (cherry picked from commit 4d75573) # Conflicts: # core/src/main/scala/chisel3/experimental/hierarchy/core/Definition.scala # core/src/main/scala/chisel3/internal/Builder.scala # src/main/scala/chisel3/stage/ChiselOptions.scala # src/main/scala/chisel3/stage/phases/AddImplicitOutputAnnotationFile.scala # src/main/scala/chisel3/stage/phases/AddImplicitOutputFile.scala # src/main/scala/chisel3/stage/phases/Convert.scala # src/main/scala/chisel3/stage/phases/Elaborate.scala # src/test/scala/circtTests/stage/ChiselStageSpec.scala * Resolve backport conflicts * MiMa waive package private constructor change * Fix ScalaDoc --------- Co-authored-by: Jack Koenig <[email protected]> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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When I tried out #4643 internally at SiFive, I realized that despite
chisel3.internal.firrtl.irbeing a package private object,ir.Circuitstill leaks out viaChiselCircuitAnnotationand it can be used freely. This leaks full access to the Chisel internal IR in a way that makes it really hard to change things.This is my attempt to "spackle" that leak by providing the new
ElaboratedCircuitAPI as the intended public interface to give to users to let them do what they want to do, while letting us muck with the internals. I think we should feel free to add and deprecate then remove APIs fromElaboratedCircuitas long as we take care to keep the actual internals private.Before merging this, I intend to test it internally and redo #4643 on top of it because I still want to backport the annotation deprecations as well. Technically #4643 does not need this, but I think this makes the story of what changes I want to make in 7.0 a lot cleaner without having to worry about changes to
ir.Circuitaccidentally breaking user code.Contributor Checklist
docs/src?Type of Improvement
Desired Merge Strategy
Release Notes
Change ChiselCircuitAnnotation and CircuitSerializationAnnotation to no longer be case classes to help with the transition to ElaboratedCircuit.
Reviewer Checklist (only modified by reviewer)
3.6.x,5.x, or6.xdepending on impact, API modification or big change:7.0)?Enable auto-merge (squash)and clean up the commit message.Create a merge commit.