Add combinatorial examples

[kboronski-ant]

This PR adds two combinatorial examples. One with 2000 LUTs (LUT4, LUT5 and LUT6),, 16 inputs and 16 outputs and another similar one, but with 3000 LUTs.

These examples have been generated with utils/generate_design.py script, which I also include in this PR.
The workflow used to generated these designs consists of the following steps:

1. run utils/generate_design.py -c <number of luts> -I number of input ports> -o <number of output ports>
2. run Vivado in tcl mode (vivado -mode tcl)
3. Load the generated netlist:

Vivado% link_design -part <part name>
Vivado% source <path to tcl file generated with utils/generate_design.py>

4. Export EDIF (must have the same name as top module which in this case is netlist_EMPTY - a default value)

Vivado% write_edif netlist_EMPTY.edif

5. Constrain ports

Vivado% place_ports
Vivado% write_xdc <path to xdc> -no_fixed_only -type physical

6. For the use with nextpnr-fpga-interchange, you can convert the EDIF to LogicalNetlist
   1. You will need a modified version of RapidWright to do that: EDIF -> LogicalNetlist converter Xilinx/RapidWright#589
   2. Invoke Rapidwright's EdifToLogicalNetlist class, which performs the conversion:

   ${RAPIDWRIGHT_PATH}/scripts/invoke_rapidwright.sh com.xilinx.rapidwright.interchange.EdifToLogicalNetlist <path to edif> <path to netlist>
   

NOTE 1: The constraint files have been manually edited to include IOSTANDARDs and allow Vivado to accept combinatorial loops.

NOTE 2: The designs include both .netlist and .edif files. Those should contain equivalent data. The .netlist files were created from the .edif netlists.