Update Instructions with riscv-opcodes #2956
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The current Instructions.scala is not up-to-date with riscv-opcodes Previous changes on this file seems to be adding new instructions manually, this can be inferred from riscv/riscv-opcodes@e2ebbf5 which changed the name from parse-opcodes to parse_opcodes thus this PR reorders a lot of instructions and CSRs
As standard instructions are synced from riscv-opcodes
Rocket already implemented NMI in chipsalliance#2711, however, riscv-opcodes currently does not have NMI as it is a WIP (See riscv/riscv-opcodes#67) To avoid generating Instructions.scala from a patched riscv-opcodes, putting NMI related insts/CSRs into CustomInstructions is reasonable.
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Related issue: dependency of #2950, but not specific to #2950 only.
General speaking, keeping synchronized with riscv-opcodes is easier to maintain.
More notes are in commit messages.
Type of change: other enhancement
Impact: API modification
Development Phase: implementation
Release Notes