remove objectmodule

src/main/scala/amba/ahb/SRAM.scala

@@ -5,15 +5,12 @@ package freechips.rocketchip.amba.ahb
 import Chisel._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{BusMemoryLogicalTreeNode, LogicalModuleTree, LogicalTreeNode}
-import freechips.rocketchip.diplomaticobjectmodel.model.AHB_Lite
 import freechips.rocketchip.util._
 import freechips.rocketchip.tilelink.LFSRNoiseMaker
 
 class AHBRAM(
     address: AddressSet,
     cacheable: Boolean = true,
-    parentLogicalTreeNode: Option[LogicalTreeNode] = None,
     executable: Boolean = true,
     beatBytes: Int = 4,
     fuzzHreadyout: Boolean = false,
@@ -37,25 +34,13 @@ class AHBRAM(
   lazy val module = new LazyModuleImp(this) with HasJustOneSeqMem {
     val (in, _) = node.in(0)
     val laneDataBits = 8
-    val (mem, omSRAM, omMem) = makeSinglePortedByteWriteSeqMem(
+    val mem = makeSinglePortedByteWriteSeqMem(
       size = BigInt(1) << mask.filter(b=>b).size,
       lanes = beatBytes,
       bits = laneDataBits)
     val eccCode = None
     val address = outer.address
 
-    parentLogicalTreeNode.map {
-      case parentLTN =>
-        def sramLogicalTreeNode = new BusMemoryLogicalTreeNode(
-          device = device,
-          omSRAMs = Seq(omSRAM),
-          busProtocol = new AHB_Lite(None),
-          dataECC = None,
-          hasAtomics = None,
-          busProtocolSpecification = None)
-        LogicalModuleTree.add(parentLTN, sramLogicalTreeNode)
-    }
-
     // The mask and address during the address phase
     val a_access    = in.htrans === AHBParameters.TRANS_NONSEQ || in.htrans === AHBParameters.TRANS_SEQ
     val a_request   = in.hready && in.hsel && a_access

src/main/scala/amba/apb/SRAM.scala

@@ -5,15 +5,12 @@ package freechips.rocketchip.amba.apb
 import Chisel._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{BusMemoryLogicalTreeNode, LogicalModuleTree, LogicalTreeNode}
-import freechips.rocketchip.diplomaticobjectmodel.model.APB
 import freechips.rocketchip.util._
 import freechips.rocketchip.tilelink.LFSRNoiseMaker
 
 class APBRAM(
     address: AddressSet,
     cacheable: Boolean = true,
-    parentLogicalTreeNode: Option[LogicalTreeNode] = None,
     executable: Boolean = true,
     beatBytes: Int = 4,
     devName: Option[String] = None,
@@ -37,25 +34,13 @@ class APBRAM(
   lazy val module = new LazyModuleImp(this) with HasJustOneSeqMem {
     val (in, _) = node.in(0)
     val laneDataBits = 8
-    val (mem, omSRAM, omMem) = makeSinglePortedByteWriteSeqMem(
+    val mem = makeSinglePortedByteWriteSeqMem(
       size = BigInt(1) << mask.filter(b=>b).size,
       lanes = beatBytes,
       bits = laneDataBits)
     val eccCode = None
     val address = outer.address
 
-    parentLogicalTreeNode.map {
-      case parentLTN =>
-        def sramLogicalTreeNode = new BusMemoryLogicalTreeNode(
-          device = device,
-          omSRAMs = Seq(omSRAM),
-          busProtocol = new APB(None),
-          dataECC = None,
-          hasAtomics = None,
-          busProtocolSpecification = None)
-        LogicalModuleTree.add(parentLTN, sramLogicalTreeNode)
-    }
-
     val paddr = Cat((mask zip (in.paddr >> log2Ceil(beatBytes)).asBools).filter(_._1).map(_._2).reverse)
     val legal = address.contains(in.paddr)
 

src/main/scala/amba/axi4/SRAM.scala

@@ -5,8 +5,6 @@ package freechips.rocketchip.amba.axi4
 import Chisel._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{BusMemoryLogicalTreeNode, LogicalModuleTree, LogicalTreeNode}
-import freechips.rocketchip.diplomaticobjectmodel.model.AXI4_Lite
 import freechips.rocketchip.util._
 import freechips.rocketchip.amba._
 
@@ -15,7 +13,6 @@ import freechips.rocketchip.amba._
 class AXI4RAM(
     address: AddressSet,
     cacheable: Boolean = true,
-    parentLogicalTreeNode: Option[LogicalTreeNode] = None,
     executable: Boolean = true,
     beatBytes: Int = 4,
     devName: Option[String] = None,
@@ -41,25 +38,13 @@ class AXI4RAM(
   lazy val module = new LazyModuleImp(this) with HasJustOneSeqMem {
     val (in, edgeIn) = node.in(0)
     val laneDataBits = 8
-    val (mem, omSRAM, omMem) = makeSinglePortedByteWriteSeqMem(
+    val mem = makeSinglePortedByteWriteSeqMem(
       size = BigInt(1) << mask.filter(b=>b).size,
       lanes = beatBytes,
       bits = laneDataBits)
     val eccCode = None
     val address = outer.address
 
-    parentLogicalTreeNode.map {
-      case parentLTN =>
-        def sramLogicalTreeNode = new BusMemoryLogicalTreeNode(
-          device = device,
-          omSRAMs = Seq(omSRAM),
-          busProtocol = new AXI4_Lite(None),
-          dataECC = None,
-          hasAtomics = None,
-          busProtocolSpecification = None)
-        LogicalModuleTree.add(parentLTN, sramLogicalTreeNode)
-    }
-
     val corrupt = if (edgeIn.bundle.requestFields.contains(AMBACorrupt)) Some(SeqMem(1 << mask.filter(b=>b).size, UInt(width=2))) else None
 
     val r_addr = Cat((mask zip (in.ar.bits.addr >> log2Ceil(beatBytes)).asBools).filter(_._1).map(_._2).reverse)
@@ -129,7 +114,6 @@ object AXI4RAM
   def apply(
     address: AddressSet,
     cacheable: Boolean = true,
-    parentLogicalTreeNode: Option[LogicalTreeNode] = None,
     executable: Boolean = true,
     beatBytes: Int = 4,
     devName: Option[String] = None,

src/main/scala/devices/debug/Debug.scala

@@ -16,7 +16,6 @@ import freechips.rocketchip.interrupts._
 import freechips.rocketchip.util._
 import freechips.rocketchip.devices.debug.systembusaccess._
 import freechips.rocketchip.devices.tilelink.TLBusBypass
-import freechips.rocketchip.diplomaticobjectmodel.logicaltree.DebugLogicalTreeNode
 import freechips.rocketchip.amba.apb.{APBToTL, APBFanout}
 import freechips.rocketchip.util.BooleanToAugmentedBoolean
 
@@ -1883,10 +1882,4 @@ class TLDebugModule(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
     io.auth.foreach { x => dmOuter.module.io.dmAuthenticated.get := x.dmAuthenticated }
     io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}}
   }
-
-  val logicalTreeNode = new DebugLogicalTreeNode(
-    device,
-    () => dmOuter,
-    () => dmInner
-  )
 }

src/main/scala/devices/debug/Periphery.scala

@@ -10,7 +10,6 @@ import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.amba.apb._
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.diplomaticobjectmodel.logicaltree.LogicalModuleTree
 import freechips.rocketchip.jtag._
 import freechips.rocketchip.util._
 import freechips.rocketchip.prci.{ClockSinkParameters, ClockSinkNode}
@@ -83,8 +82,6 @@ trait HasPeripheryDebug { this: BaseSubsystem =>
   val debugOpt = p(DebugModuleKey).map { params =>
     val debug = LazyModule(new TLDebugModule(tlbus.beatBytes))
 
-    LogicalModuleTree.add(logicalTreeNode, debug.logicalTreeNode)
-
     debug.node := tlbus.coupleTo("debug"){ TLFragmenter(tlbus) := _ }
     debug.dmInner.dmInner.customNode := debugCustomXbarOpt.get.node
 

src/main/scala/devices/tilelink/CLINT.scala

@@ -5,8 +5,6 @@ package freechips.rocketchip.devices.tilelink
 import Chisel._
 import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.diplomaticobjectmodel.logicaltree._
-import freechips.rocketchip.diplomaticobjectmodel.model._
 import freechips.rocketchip.interrupts._
 import freechips.rocketchip.regmapper._
 import freechips.rocketchip.subsystem._
@@ -89,7 +87,7 @@ class CLINT(params: CLINTParams, beatBytes: Int)(implicit p: Parameters) extends
      * bffc mtime hi
      */
 
-    val omRegMap : OMRegisterMap = node.regmap(
+    node.regmap(
       0                -> RegFieldGroup ("msip", Some("MSIP Bits"), ipi.zipWithIndex.flatMap{ case (r, i) =>
         RegField(1, r, RegFieldDesc(s"msip_$i", s"MSIP bit for Hart $i", reset=Some(0))) :: RegField(ipiWidth - 1) :: Nil }),
       timecmpOffset(0) -> timecmp.zipWithIndex.flatMap{ case (t, i) => RegFieldGroup(s"mtimecmp_$i", Some(s"MTIMECMP for hart $i"),
@@ -98,16 +96,13 @@ class CLINT(params: CLINTParams, beatBytes: Int)(implicit p: Parameters) extends
         RegField.bytes(time, Some(RegFieldDesc("mtime", "", reset=Some(0), volatile=true))))
     )
   }
-
-  def logicalTreeNode: CLINTLogicalTreeNode = new CLINTLogicalTreeNode(device, module.omRegMap)
 }
 
 /** Trait that will connect a CLINT to a subsystem */
 trait CanHavePeripheryCLINT { this: BaseSubsystem =>
   val clintOpt = p(CLINTKey).map { params =>
     val tlbus = locateTLBusWrapper(p(CLINTAttachKey).slaveWhere)
     val clint = LazyModule(new CLINT(params, cbus.beatBytes))
-    LogicalModuleTree.add(logicalTreeNode, clint.logicalTreeNode)
     clint.node := tlbus.coupleTo("clint") { TLFragmenter(tlbus) := _ }
 
     // Override the implicit clock and reset -- could instead include a clockNode in the clint, and make it a RawModuleImp?

src/main/scala/devices/tilelink/Error.scala

@@ -7,32 +7,12 @@ import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 
-import freechips.rocketchip.diplomaticobjectmodel.{DiplomaticObjectModelAddressing, HasLogicalTreeNode}
-import freechips.rocketchip.diplomaticobjectmodel.logicaltree.LogicalTreeNode
-import freechips.rocketchip.diplomaticobjectmodel.model.{OMErrorDevice, OMComponent}
-
 /** Adds a /dev/null slave that generates TL error response messages */
 class TLError(params: DevNullParams, buffer: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters)
     extends DevNullDevice(params,
       minLatency = if (buffer) 1 else 0,
       beatBytes, new SimpleDevice("error-device", Seq("sifive,error0")))
-    with HasLogicalTreeNode
 {
-  lazy val logicalTreeNode: LogicalTreeNode = new LogicalTreeNode(() => Some(device)) {
-    def getOMComponents(resourceBindings: ResourceBindings, children: Seq[OMComponent] = Nil) = {
-      val Description(name, mapping) = device.describe(resourceBindings)
-      val memRegions = DiplomaticObjectModelAddressing.getOMMemoryRegions(name, resourceBindings, None)
-      val interrupts = DiplomaticObjectModelAddressing.describeInterrupts(name, resourceBindings)
-      Seq(OMErrorDevice(
-        memoryRegions = memRegions.map(_.copy(
-          name = "errordevice",
-          description = "Error Device"
-        )),
-        interrupts = interrupts
-      ))
-    }
-  }
-
   lazy val module = new LazyModuleImp(this) {
     import TLMessages._
     import TLPermissions._

src/main/scala/devices/tilelink/Plic.scala

@@ -15,7 +15,6 @@ import freechips.rocketchip.util._
 import freechips.rocketchip.util.property
 import freechips.rocketchip.prci.{ClockSinkDomain}
 import chisel3.internal.sourceinfo.SourceInfo
-import freechips.rocketchip.diplomaticobjectmodel.model._
 
 import scala.math.min
 
@@ -306,7 +305,7 @@ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends
       )
     }
 
-    val omRegMap : OMRegisterMap = node.regmap((priorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_*)
+    node.regmap((priorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_*)
 
     if (nDevices >= 2) {
       val claimed = claimer(0) && maxDevs(0) > 0

src/main/scala/devices/tilelink/Zero.scala

@@ -7,10 +7,6 @@ import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink.TLMessages
 
-import freechips.rocketchip.diplomaticobjectmodel.{DiplomaticObjectModelAddressing, HasLogicalTreeNode}
-import freechips.rocketchip.diplomaticobjectmodel.logicaltree.LogicalTreeNode
-import freechips.rocketchip.diplomaticobjectmodel.model.{OMZeroDevice, OMComponent}
-
 /** This /dev/null device accepts single beat gets/puts, as well as atomics.
   * Response data is always 0. Reequests to write data have no effect.
   */
@@ -27,24 +23,7 @@ class TLZero(address: AddressSet, beatBytes: Int = 4)(implicit p: Parameters)
     minLatency = 1,
     beatBytes = beatBytes,
     device = new SimpleDevice("rom", Seq("ucbbar,cacheable-zero0")))
-    with HasLogicalTreeNode
 {
-
-  lazy val logicalTreeNode: LogicalTreeNode = new LogicalTreeNode(() => Some(device)) {
-    def getOMComponents(resourceBindings: ResourceBindings, children: Seq[OMComponent] = Nil) = {
-      val Description(name, mapping) = device.describe(resourceBindings)
-      val memRegions = DiplomaticObjectModelAddressing.getOMMemoryRegions(name, resourceBindings, None)
-      val interrupts = DiplomaticObjectModelAddressing.describeInterrupts(name, resourceBindings)
-      Seq(OMZeroDevice(
-        memoryRegions = memRegions.map(_.copy(
-          name = "zerodevice",
-          description = "Zero Device"
-        )),
-        interrupts = interrupts
-      ))
-    }
-  }
-
   lazy val module = new LazyModuleImp(this) {
     val (in, edge) = node.in(0)
 

src/main/scala/diplomacy/SRAM.scala

@@ -5,8 +5,6 @@ package freechips.rocketchip.diplomacy
 import Chisel._
 import chisel3.SyncReadMem
 import freechips.rocketchip.config.Parameters
-import freechips.rocketchip.diplomaticobjectmodel.DiplomaticObjectModelAddressing
-import freechips.rocketchip.diplomaticobjectmodel.model._
 import freechips.rocketchip.util.{DescribedSRAM, Code}
 
 abstract class DiplomaticSRAM(
@@ -19,10 +17,6 @@ abstract class DiplomaticSRAM(
     .map(new SimpleDevice(_, dtsCompat.getOrElse(Seq("sifive,sram0"))))
     .getOrElse(new MemoryDevice())
 
-  def getOMMemRegions(resourceBindings: ResourceBindings): Seq[OMMemoryRegion] = {
-    DiplomaticObjectModelAddressing.getOMMemoryRegions(devName.getOrElse(""), resourceBindings) // TODO name source???
-  }
-
   val resources = device.reg("mem")
 
   def bigBits(x: BigInt, tail: List[Boolean] = Nil): List[Boolean] =
@@ -34,21 +28,15 @@ abstract class DiplomaticSRAM(
   def makeSinglePortedByteWriteSeqMem(size: BigInt, lanes: Int = beatBytes, bits: Int = 8) = {
     // We require the address range to include an entire beat (for the write mask)
 
-    val (mem, omSRAM) =  DescribedSRAM(
+    val mem  =  DescribedSRAM(
       name = devName.getOrElse("mem"),
       desc = devName.getOrElse("mem"),
       size = size,
       data = Vec(lanes, UInt(width = bits))
     )
     devName.foreach(n => mem.suggestName(n.split("-").last))
 
-    val omMem: OMMemory = DiplomaticObjectModelAddressing.makeOMMemory(
-      desc = "mem", //lim._2.name.map(n => n).getOrElse(lim._1.name),
-      depth = size,
-      data = Vec(lanes, UInt(width = bits))
-    )
-
-    (mem, omSRAM, Seq(omMem))
+    mem
   }
 }