allow usage declarations (for unique names)

All CondAssign should be reg etc.
clash-lang · Jun 27, 2022 · 1c8d33c · 1c8d33c
1 parent 619cb8b
commit 1c8d33c
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Showing 5 changed files with 15 additions and 3 deletions.
diff --git a/clash-lib/src/Clash/Backend.hs b/clash-lib/src/Clash/Backend.hs
@@ -14,6 +14,7 @@ module Clash.Backend where
 
 import Data.HashMap.Strict                  (HashMap, empty)
 import Data.HashSet                         (HashSet)
+import Control.Lens                         (Lens')
 import Data.Monoid                          (Ap)
 import Data.Text                            (Text)
 import qualified Data.Text.Lazy             as LT
@@ -167,3 +168,4 @@ class HasIdentifierSet state => Backend state where
   domainConfigurations :: State state DomainMap
   -- | Set the domain configurations
   setDomainConfigurations :: DomainMap -> state -> state
+  usageMap :: Lens' state UsageMap
diff --git a/clash-lib/src/Clash/Backend/SystemVerilog.hs b/clash-lib/src/Clash/Backend/SystemVerilog.hs
@@ -195,6 +195,7 @@ instance Backend SystemVerilogState where
   renderEnums = use renderEnums_
   domainConfigurations = use domainConfigurations_
   setDomainConfigurations confs s = s {_domainConfigurations_ = confs}
+  usageMap = usages
 
 type SystemVerilogM a = Ap (State SystemVerilogState) a
 

diff --git a/clash-lib/src/Clash/Backend/VHDL.hs b/clash-lib/src/Clash/Backend/VHDL.hs
@@ -284,6 +284,7 @@ instance Backend VHDLState where
   renderEnums = use renderEnums_
   domainConfigurations = use domainConfigurations_
   setDomainConfigurations confs s = s {_domainConfigurations_ = confs}
+  usageMap = usages
 
 type VHDLM a = Ap (State VHDLState) a
 

diff --git a/clash-lib/src/Clash/Backend/Verilog.hs b/clash-lib/src/Clash/Backend/Verilog.hs
@@ -195,6 +195,7 @@ instance Backend VerilogState where
   renderEnums = pure (RenderEnums False)
   domainConfigurations = use domainConfigurations_
   setDomainConfigurations confs s = s {_domainConfigurations_ = confs}
+  usageMap = usages
 
 type VerilogM a = Ap (State VerilogState) a
 

diff --git a/clash-lib/src/Clash/Primitives/DSL.hs b/clash-lib/src/Clash/Primitives/DSL.hs
@@ -91,6 +91,7 @@ import           Data.IntMap                     (IntMap)
 import qualified Data.IntMap                     as IntMap
 import           Data.List                       (intersperse)
 import           Data.List.Extra                 (zipEqual)
+import qualified Data.Map                        as Map
 import           Data.Maybe                      (fromMaybe)
 import           Data.Monoid                     (Ap(getAp))
 import           Data.Semigroup                  hiding (Product)
@@ -102,15 +103,15 @@ import           Data.Text.Prettyprint.Doc.Extra
 import           GHC.Stack                       (HasCallStack)
 
 import           Clash.Annotations.Primitive     (HDL (..), Primitive (..))
-import           Clash.Backend                   hiding (fromBV, toBV)
+import           Clash.Backend                   hiding (Usage, fromBV, toBV)
 import           Clash.Backend.VHDL              (VHDLState)
 import           Clash.Core.Var                  (Attr')
 import           Clash.Netlist.BlackBox.Util     (exprToString, renderElem)
 import           Clash.Netlist.BlackBox.Types
   (BlackBoxTemplate, Element(Component, Text), Decl(..))
 import qualified Clash.Netlist.Id                as Id
-import           Clash.Netlist.Types             hiding (Component, toBit)
-import           Clash.Netlist.Util
+import           Clash.Netlist.Types             hiding (Component, toBit, usageMap)
+import           Clash.Netlist.Util              hiding (declareUse)
 import           Clash.Util                      (clogBase)
 import qualified Data.String.Interpolate         as I
 import           Data.String.Interpolate.Util    (unindent)
@@ -415,6 +416,7 @@ boolToBit bitName = \case
         [ (Just (BoolLit True), Literal Nothing (BitLit H))
         , (Nothing            , Literal Nothing (BitLit L))
         ]
+    declareUse (Proc Blocking) uniqueBitName
     pure texp
   tExpr -> error $ "boolToBit: Got \"" <> show tExpr <> "\" expected Bool"
 
@@ -434,9 +436,13 @@ enableToBit bitName = \case
         [ (Just (BoolLit True), Literal Nothing (BitLit H))
         , (Nothing            , Literal Nothing (BitLit L))
         ]
+    declareUse (Proc Blocking) uniqueBitName
     pure texp
   tExpr -> error $ "enableToBit: Got \"" <> show tExpr <> "\" expected Enable"
 
+declareUse :: Backend backend => Usage -> Identifier -> State (BlockState backend) ()
+declareUse u i = bsBackend.usageMap %= Map.insert (Id.toText i) u
+
 -- | Use to create an output `Bool` from a `Bit`. The expression given
 --   must be the identifier of the bool you wish to get assigned.
 --   Returns a reference to a declared `Bit` that should get assigned
@@ -457,6 +463,7 @@ boolFromBit boolName = \case
         [ (Just (BitLit H), Literal Nothing (BoolLit True))
         , (Nothing        , Literal Nothing (BoolLit False))
         ]
+    declareUse (Proc Blocking) uniqueBoolName
     pure texp
   tExpr -> error $ "boolFromBit: Got \"" <> show tExpr <> "\" expected Bit"