Revert "Disallow implicit nets in (System)Verilog (#2174)"

This reverts commit 753f583.
clash-lang · May 12, 2022 · 4370a42 · 4370a42
1 parent 1b0efcc
commit 4370a42
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Showing 5 changed files with 6 additions and 20 deletions.
diff --git a/changelog/2022-04-21T11_24_14+02_00_no_default_nettype.md b/changelog/2022-04-21T11_24_14+02_00_no_default_nettype.md
diff --git a/clash-lib/src/Clash/Backend/SystemVerilog.hs b/clash-lib/src/Clash/Backend/SystemVerilog.hs
@@ -217,14 +217,12 @@ genSystemVerilog _ sp seen c = do
   where
     cName   = componentName c
     verilog = commentHeader <> line <>
-              nettype <> line <>
               timescale <> line <>
               module_ c
     commentHeader
          = "/* AUTOMATICALLY GENERATED SYSTEMVERILOG-2005 SOURCE CODE."
       <> line <> "** GENERATED BY CLASH " <> string (Text.pack clashVer) <> ". DO NOT MODIFY."
       <> line <> "*/"
-    nettype = "`default_nettype none"
     timescale = "`timescale 100fs/100fs"
 
 -- | Generate a SystemVerilog package containing type definitions for the given HWTypes
@@ -526,19 +524,11 @@ module_ c =
   inPorts  = sequence [ sigPort (Nothing,isBiSignalIn ty) (i,ty) Nothing | (i,ty)  <- inputs c  ]
   outPorts = sequence [ sigPort (Just wr,False) p iEM | (wr, p, iEM) <- outputs c ]
 
-  -- NOTE [net types and data types]
-  --
-  -- SystemVerilog makes a distinction between the type of a net and the data
-  -- type of a signal. For output ports / inout ports this is fine, as there
-  -- is only one possible type. For input ports when using `default_nettype none
-  -- we have to specify the net type as wire explicitly (or vendor tools will
-  -- claim the net from the port declaration is implicitly defined).
-
   wr2ty (Nothing,isBidirectional)
     | isBidirectional
     = "inout"
     | otherwise
-    = "input wire" -- See NOTE [net types and data types]
+    = "input"
   wr2ty (Just _,_)
     = "output"
 

diff --git a/clash-lib/src/Clash/Backend/Verilog.hs b/clash-lib/src/Clash/Backend/Verilog.hs
@@ -210,7 +210,7 @@ genVerilog sp seen c = do
     Ap $ idSeen %= Id.union seen
 
     Ap (setSrcSpan sp)
-    v    <- commentHeader <> line <> nettype <> line <> timescale <> line <> module_ c
+    v    <- commentHeader <> line <> timescale <> line <> module_ c
     incs <- Ap $ use includes
     return ((TextS.unpack (Id.toText cName), v), incs)
   where
@@ -219,7 +219,6 @@ genVerilog sp seen c = do
          = "/* AUTOMATICALLY GENERATED VERILOG-2001 SOURCE CODE."
       <> line <> "** GENERATED BY CLASH " <> string (Text.pack clashVer) <> ". DO NOT MODIFY."
       <> line <> "*/"
-    nettype = "`default_nettype none"
     timescale = "`timescale 100fs/100fs"
 
 sigPort

diff --git a/tests/shouldwork/Issues/T1171.hs b/tests/shouldwork/Issues/T1171.hs
@@ -55,4 +55,4 @@ mainSystemVerilog = do
   [topDir] <- getArgs
   content  <- readFile (topDir </> show 'f </> "f.sv")
 
-  assertIn "input wire logic en  // enable" content
+  assertIn "input logic en  // enable" content
diff --git a/tests/shouldwork/SynthesisAttributes/T1771.hs b/tests/shouldwork/SynthesisAttributes/T1771.hs
@@ -63,6 +63,6 @@ mainSystemVerilog = do
   [topDir] <- getArgs
   content <- readFile (topDir </> show 'topEntity </> "topEntity.sv")
 
-  assertIn "(* foo = \"AA\" *) input wire logic [0:0] pin_a" content
-  assertIn "(* foo = \"BB\", bar = 1 *) input wire logic [0:0] pin_b" content
-  assertIn "(* foo = \"CC\" *) input wire logic [0:0] pin_c" content
+  assertIn "(* foo = \"AA\" *) input logic [0:0] pin_a" content
+  assertIn "(* foo = \"BB\", bar = 1 *) input logic [0:0] pin_b" content
+  assertIn "(* foo = \"CC\" *) input logic [0:0] pin_c" content