add file for dcfifo

clash-lang · May 11, 2022 · 6d50a4a · 6d50a4a
1 parent efa8695
commit 6d50a4a
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Showing 3 changed files with 64 additions and 11 deletions.
diff --git a/tests/Main.hs b/tests/Main.hs
@@ -428,17 +428,18 @@ runClashTest = defaultMain $ clashTestRoot
       -- The Cores.Xilinx.Floating tests require Vivado (and take much time to
       -- run).
       --
-      -- , clashTestGroup "Cores"
-      --   [ clashTestGroup "Xilinx"
-      --     [ runTest "Floating" def{ clashFlags=["-fclash-float-support"]
-      --                             , buildTargets=[ "addBasicTB"
-      --                                            , "addEnableTB"
-      --                                            , "addShortPLTB"
-      --                                            , "subBasicTB"
-      --                                            , "mulBasicTB"
-      --                                            , "divBasicTB"]}
-      --     ]
-      --   ]
+      , clashTestGroup "Cores"
+        [ clashTestGroup "Xilinx"
+          -- [ runTest "Floating" def{ clashFlags=["-fclash-float-support"]
+                                  -- , buildTargets=[ "addBasicTB"
+                                                 -- , "addEnableTB"
+                                                 -- , "addShortPLTB"
+                                                 -- , "subBasicTB"
+                                                 -- , "mulBasicTB"
+                                                 -- , "divBasicTB"]}
+          [ runTest "DcFifoTop" def
+          ]
+        ]
       , clashTestGroup "CSignal"
         [ runTest "MAC" def{hdlSim=False}
         , runTest "CBlockRamTest" def{hdlSim=False}

diff --git a/tests/shouldwork/Cores/Xilinx/DcFifo.hs b/tests/shouldwork/Cores/Xilinx/DcFifo.hs
@@ -0,0 +1,32 @@
+module DcFifo where
+
+import Clash.Explicit.Prelude
+import Clash.Explicit.Testbench
+
+import Data.Word (Word32)
+
+import Clash.Cores.Xilinx.DcFifo.Explicit
+
+createDomain vSystem{vName="P30", vPeriod=30000}
+createDomain vSystem{vName="P50", vPeriod=50000}
+
+tbOutput
+  :: Clock P50
+  -> Clock P30
+  -> Signal P30 (BitVector 32)
+tbOutput wClk rClk = ignoreFor rClk resetGen enableGen d2 0 fifoOut
+  where
+    (XilinxFifo _ _ _ rdRstBusy isEmpty _ fifoOut) = dcFifo @4 defConfig wClk rClk resetGen inpSignal wrEna rdEna
+    inpSignal = pure (pack (0xFFFF :: Word32))
+    wrEna = pure True
+    rdEna = pure True
+
+tb
+  :: (KnownNat n, 1 <= n)
+  => Vec n (BitVector 32)
+  -> Signal P30 Bool
+tb expected = done
+  where
+    output = tbOutput wClk rClk
+    (rClk, wClk) = (clockGen, clockGen) -- biTbClockGen (not <$> done) :: (Clock P30, Clock P50)
+    done = outputVerifier' rClk resetGen expected output
diff --git a/tests/shouldwork/Cores/Xilinx/DcFifoTop.hs b/tests/shouldwork/Cores/Xilinx/DcFifoTop.hs
@@ -0,0 +1,20 @@
+module DcFifoTop where
+
+import Clash.Explicit.Prelude
+
+import Clash.Cores.Xilinx.DcFifo.Explicit
+
+import DcFifo
+
+topEntity
+  :: Clock P50
+  -> Clock P30
+  -> Signal P50 (BitVector 32)
+  -> Signal P50 Bool
+  -> Signal P30 Bool
+  -> XilinxFifo P30 P50 7 32
+topEntity wClk rdClk = dcFifo defConfig wClk rdClk resetGen
+{-# NOINLINE topEntity #-}
+
+testBench :: Signal P30 Bool
+testBench = tb $(listToVecTH $ sampleN 20 $ tbOutput clockGen clockGen)