Version 2.19.0-437.0.dev

Merge 4f92510 into dev

runtime/platform/utils.cc

@@ -14,21 +14,6 @@
 
 namespace dart {
 
-// Implementation is from "Hacker's Delight" by Henry S. Warren, Jr.,
-// figure 3-3, page 48, where the function is called clp2.
-uintptr_t Utils::RoundUpToPowerOfTwo(uintptr_t x) {
-  x = x - 1;
-  x = x | (x >> 1);
-  x = x | (x >> 2);
-  x = x | (x >> 4);
-  x = x | (x >> 8);
-  x = x | (x >> 16);
-#if defined(ARCH_IS_64_BIT)
-  x = x | (x >> 32);
-#endif  // defined(ARCH_IS_64_BIT)
-  return x + 1;
-}
-
 int Utils::CountLeadingZeros64(uint64_t x) {
 #if defined(ARCH_IS_32_BIT)
   const uint32_t x_hi = static_cast<uint32_t>(x >> 32);

runtime/platform/utils.h

@@ -114,7 +114,20 @@ class Utils {
         RoundUp(reinterpret_cast<uword>(x), alignment, offset));
   }
 
-  static uintptr_t RoundUpToPowerOfTwo(uintptr_t x);
+  // Implementation is from "Hacker's Delight" by Henry S. Warren, Jr.,
+  // figure 3-3, page 48, where the function is called clp2.
+  static constexpr uintptr_t RoundUpToPowerOfTwo(uintptr_t x) {
+    x = x - 1;
+    x = x | (x >> 1);
+    x = x | (x >> 2);
+    x = x | (x >> 4);
+    x = x | (x >> 8);
+    x = x | (x >> 16);
+#if defined(ARCH_IS_64_BIT)
+    x = x | (x >> 32);
+#endif  // defined(ARCH_IS_64_BIT)
+    return x + 1;
+  }
 
   static constexpr int CountOneBits64(uint64_t x) {
     // Apparently there are x64 chips without popcount.

runtime/vm/app_snapshot.cc

@@ -6052,7 +6052,8 @@ class VMSerializationRoots : public SerializationRoots {
     s->AddBaseObject(Object::transition_sentinel().ptr(), "Null",
                      "transition_sentinel");
     s->AddBaseObject(Object::empty_array().ptr(), "Array", "<empty_array>");
-    s->AddBaseObject(Object::zero_array().ptr(), "Array", "<zero_array>");
+    s->AddBaseObject(Object::empty_instantiations_cache_array().ptr(), "Array",
+                     "<empty_instantiations_cache_array>");
     s->AddBaseObject(Object::dynamic_type().ptr(), "Type", "<dynamic type>");
     s->AddBaseObject(Object::void_type().ptr(), "Type", "<void type>");
     s->AddBaseObject(Object::empty_type_arguments().ptr(), "TypeArguments",
@@ -6174,7 +6175,7 @@ class VMDeserializationRoots : public DeserializationRoots {
     d->AddBaseObject(Object::sentinel().ptr());
     d->AddBaseObject(Object::transition_sentinel().ptr());
     d->AddBaseObject(Object::empty_array().ptr());
-    d->AddBaseObject(Object::zero_array().ptr());
+    d->AddBaseObject(Object::empty_instantiations_cache_array().ptr());
     d->AddBaseObject(Object::dynamic_type().ptr());
     d->AddBaseObject(Object::void_type().ptr());
     d->AddBaseObject(Object::empty_type_arguments().ptr());

runtime/vm/compiler/assembler/assembler_arm.cc

@@ -2249,7 +2249,7 @@ void Assembler::LoadCompressedSmi(Register dest, const Address& slot) {
   ldr(dest, slot);
 #if defined(DEBUG)
   Label done;
-  BranchIfSmi(dest, &done);
+  BranchIfSmi(dest, &done, kNearJump);
   Stop("Expected Smi");
   Bind(&done);
 #endif

runtime/vm/compiler/assembler/assembler_arm.h

@@ -409,11 +409,13 @@ class Assembler : public AssemblerBase {
     LoadFromOffset(dst, base, offset);
   }
   void LoadCompressed(Register dest, const Address& slot) { ldr(dest, slot); }
-  void LoadCompressedSmi(Register dest, const Address& slot);
+  void LoadCompressedSmi(Register dest, const Address& slot) override;
   void StoreMemoryValue(Register src, Register base, int32_t offset) {
     StoreToOffset(src, base, offset);
   }
-  void LoadAcquire(Register dst, Register address, int32_t offset = 0) {
+  void LoadAcquire(Register dst,
+                   Register address,
+                   int32_t offset = 0) override {
     ldr(dst, Address(address, offset));
     dmb();
   }
@@ -858,6 +860,15 @@ class Assembler : public AssemblerBase {
   void AndImmediate(Register rd, int32_t imm, Condition cond = AL) {
     AndImmediate(rd, rd, imm, cond);
   }
+  void AndRegisters(Register dst,
+                    Register src1,
+                    Register src2 = kNoRegister) override {
+    ASSERT(src1 != src2);  // Likely a mistake.
+    if (src2 == kNoRegister) {
+      src2 = dst;
+    }
+    and_(dst, src2, Operand(src1));
+  }
   void OrImmediate(Register rd, Register rs, int32_t imm, Condition cond = AL);
   void OrImmediate(Register rd, int32_t imm, Condition cond = AL) {
     OrImmediate(rd, rd, imm, cond);
@@ -881,7 +892,13 @@ class Assembler : public AssemblerBase {
   void TestImmediate(Register rn, int32_t imm, Condition cond = AL);
 
   // Compare rn with signed immediate value. May clobber IP.
-  void CompareImmediate(Register rn, int32_t value, Condition cond = AL);
+  void CompareImmediate(Register rn, int32_t value, Condition cond);
+  void CompareImmediate(Register rn,
+                        int32_t value,
+                        OperandSize width = kFourBytes) override {
+    ASSERT_EQUAL(width, kFourBytes);
+    CompareImmediate(rn, value, AL);
+  }
 
   // Signed integer division of left by right. Checks to see if integer
   // division is supported. If not, uses the FPU for division with
@@ -1435,6 +1452,12 @@ class Assembler : public AssemblerBase {
                                     Register instance,
                                     Register offset_in_words_as_smi);
 
+  void LoadFieldAddressForOffset(Register address,
+                                 Register instance,
+                                 int32_t offset) override {
+    AddImmediate(address, instance, offset - kHeapObjectTag);
+  }
+
   void LoadHalfWordUnaligned(Register dst, Register addr, Register tmp);
   void LoadHalfWordUnsignedUnaligned(Register dst, Register addr, Register tmp);
   void StoreHalfWordUnaligned(Register src, Register addr, Register tmp);

runtime/vm/compiler/assembler/assembler_arm64.cc

@@ -972,7 +972,7 @@ void Assembler::LoadCompressedSmi(Register dest, const Address& slot) {
 #endif
 #if defined(DEBUG)
   Label done;
-  BranchIfSmi(dest, &done);
+  BranchIfSmi(dest, &done, kNearJump);
   Stop("Expected Smi");
   Bind(&done);
 #endif

runtime/vm/compiler/assembler/assembler_arm64.h

@@ -574,7 +574,9 @@ class Assembler : public AssemblerBase {
   void TsanStoreRelease(Register addr);
 #endif
 
-  void LoadAcquire(Register dst, Register address, int32_t offset = 0) {
+  void LoadAcquire(Register dst,
+                   Register address,
+                   int32_t offset = 0) override {
     if (offset != 0) {
       AddImmediate(TMP2, address, offset);
       ldar(dst, TMP2);
@@ -591,7 +593,7 @@ class Assembler : public AssemblerBase {
 
   void LoadAcquireCompressed(Register dst,
                              Register address,
-                             int32_t offset = 0) {
+                             int32_t offset = 0) override {
     if (offset != 0) {
       AddImmediate(TMP2, address, offset);
       ldar(dst, TMP2, kObjectBytes);
@@ -1839,6 +1841,15 @@ class Assembler : public AssemblerBase {
   void AndImmediate(Register rd, int64_t imm) {
     AndImmediate(rd, rd, imm);
   }
+  void AndRegisters(Register dst,
+                    Register src1,
+                    Register src2 = kNoRegister) override {
+    ASSERT(src1 != src2);  // Likely a mistake.
+    if (src2 == kNoRegister) {
+      src2 = dst;
+    }
+    and_(dst, src2, Operand(src1));
+  }
   void OrImmediate(Register rd,
                    Register rn,
                    int64_t imm,
@@ -1851,7 +1862,9 @@ class Assembler : public AssemblerBase {
                     int64_t imm,
                     OperandSize sz = kEightBytes);
   void TestImmediate(Register rn, int64_t imm, OperandSize sz = kEightBytes);
-  void CompareImmediate(Register rn, int64_t imm, OperandSize sz = kEightBytes);
+  void CompareImmediate(Register rn,
+                        int64_t imm,
+                        OperandSize sz = kEightBytes) override;
 
   Address PrepareLargeOffset(Register base, int32_t offset, OperandSize sz);
   void LoadFromOffset(Register dest,
@@ -1967,7 +1980,7 @@ class Assembler : public AssemblerBase {
 
   void LoadCompressed(Register dest, const Address& slot);
   void LoadCompressedFromOffset(Register dest, Register base, int32_t offset);
-  void LoadCompressedSmi(Register dest, const Address& slot);
+  void LoadCompressedSmi(Register dest, const Address& slot) override;
   void LoadCompressedSmiFromOffset(Register dest,
                                    Register base,
                                    int32_t offset);
@@ -2300,6 +2313,12 @@ class Assembler : public AssemblerBase {
                                     Register instance,
                                     Register offset_in_words_as_smi);
 
+  void LoadFieldAddressForOffset(Register address,
+                                 Register instance,
+                                 int32_t offset) override {
+    AddImmediate(address, instance, offset - kHeapObjectTag);
+  }
+
   // Returns object data offset for address calculation; for heap objects also
   // accounts for the tag.
   static int32_t HeapDataOffset(bool is_external, intptr_t cid) {

runtime/vm/compiler/assembler/assembler_base.h

@@ -709,6 +709,12 @@ class AssemblerBase : public StackResource {
     kRelaxedNonAtomic,
   };
 
+  virtual void LoadAcquire(Register reg, Register address, int32_t offset) = 0;
+
+  virtual void LoadFieldAddressForOffset(Register reg,
+                                         Register base,
+                                         int32_t offset) = 0;
+
   virtual void LoadField(Register dst, const FieldAddress& address) = 0;
   virtual void LoadFieldFromOffset(Register reg,
                                    Register base,
@@ -732,10 +738,17 @@ class AssemblerBase : public StackResource {
   void StoreToSlot(Register src, Register base, const Slot& slot);
   void StoreToSlotNoBarrier(Register src, Register base, const Slot& slot);
 
+  // Loads a Smi, handling sign extension appropriately when compressed.
+  // In DEBUG mode, also checks that the loaded value is a Smi and halts if not.
+  virtual void LoadCompressedSmi(Register dst, const Address& slot) = 0;
+
   // Install pure virtual methods if using compressed pointers, to ensure that
   // these methods are overridden. If there are no compressed pointers, forward
   // to the uncompressed version.
 #if defined(DART_COMPRESSED_POINTERS)
+  virtual void LoadAcquireCompressed(Register dst,
+                                     Register address,
+                                     int32_t offset) = 0;
   virtual void LoadCompressedField(Register dst,
                                    const FieldAddress& address) = 0;
   virtual void LoadCompressedFieldFromOffset(Register dst,
@@ -753,6 +766,11 @@ class AssemblerBase : public StackResource {
       Register value,       // Value we are storing.
       MemoryOrder memory_order = kRelaxedNonAtomic) = 0;
 #else
+  virtual void LoadAcquireCompressed(Register dst,
+                                     Register address,
+                                     int32_t offset) {
+    LoadAcquire(dst, address, offset);
+  }
   virtual void LoadCompressedField(Register dst, const FieldAddress& address) {
     LoadField(dst, address);
   }
@@ -790,8 +808,16 @@ class AssemblerBase : public StackResource {
                                                   /*Nullability*/ int8_t value,
                                                   Register scratch) = 0;
 
+  virtual void CompareImmediate(Register reg,
+                                target::word imm,
+                                OperandSize width = kWordBytes) = 0;
   virtual void LsrImmediate(Register dst, int32_t shift) = 0;
 
+  // If src2 == kNoRegister, dst = dst & src1, otherwise dst = src1 & src2.
+  virtual void AndRegisters(Register dst,
+                            Register src1,
+                            Register src2 = kNoRegister) = 0;
+
   void LoadTypeClassId(Register dst, Register src) {
 #if !defined(TARGET_ARCH_IA32)
     EnsureHasClassIdInDEBUG(kTypeCid, src, TMP);

runtime/vm/compiler/assembler/assembler_ia32.cc

@@ -1943,6 +1943,21 @@ void Assembler::SubImmediate(Register reg, const Immediate& imm) {
   }
 }
 
+void Assembler::AndRegisters(Register dst, Register src1, Register src2) {
+  ASSERT(src1 != src2);  // Likely a mistake.
+  if (src2 == kNoRegister) {
+    src2 = dst;
+  }
+  if (dst == src2) {
+    andl(dst, src1);
+  } else if (dst == src1) {
+    andl(dst, src2);
+  } else {
+    movl(dst, src1);
+    andl(dst, src2);
+  }
+}
+
 void Assembler::Drop(intptr_t stack_elements) {
   ASSERT(stack_elements >= 0);
   if (stack_elements > 0) {
@@ -2022,6 +2037,16 @@ void Assembler::CompareObject(Register reg, const Object& object) {
   }
 }
 
+void Assembler::LoadCompressedSmi(Register dest, const Address& slot) {
+  movl(dest, slot);
+#if defined(DEBUG)
+  Label done;
+  BranchIfSmi(dest, &done, kNearJump);
+  Stop("Expected Smi");
+  Bind(&done);
+#endif
+}
+
 void Assembler::StoreIntoObject(Register object,
                                 const Address& dest,
                                 Register value,

runtime/vm/compiler/assembler/assembler_ia32.h

@@ -707,7 +707,9 @@ class Assembler : public AssemblerBase {
     }
   }
 
-  void LoadAcquire(Register dst, Register address, int32_t offset = 0) {
+  void LoadAcquire(Register dst,
+                   Register address,
+                   int32_t offset = 0) override {
     // On intel loads have load-acquire behavior (i.e. loads are not re-ordered
     // with other loads).
     movl(dst, Address(address, offset));
@@ -763,6 +765,9 @@ class Assembler : public AssemblerBase {
   void AndImmediate(Register dst, int32_t value) {
     andl(dst, Immediate(value));
   }
+  void AndRegisters(Register dst,
+                    Register src1,
+                    Register src2 = kNoRegister) override;
   void OrImmediate(Register dst, int32_t value) {
     orl(dst, Immediate(value));
   }
@@ -773,7 +778,10 @@ class Assembler : public AssemblerBase {
     shrl(dst, Immediate(shift));
   }
 
-  void CompareImmediate(Register reg, int32_t immediate) {
+  void CompareImmediate(Register reg,
+                        int32_t immediate,
+                        OperandSize width = kFourBytes) override {
+    ASSERT_EQUAL(width, kFourBytes);
     cmpl(reg, Immediate(immediate));
   }
 
@@ -812,6 +820,7 @@ class Assembler : public AssemblerBase {
   void CompareObject(Register reg, const Object& object);
 
   void LoadCompressed(Register dest, const Address& slot) { movl(dest, slot); }
+  void LoadCompressedSmi(Register dst, const Address& slot) override;
 
   // Store into a heap object and apply the generational write barrier. (Unlike
   // the other architectures, this does not apply the incremental write barrier,
@@ -1029,6 +1038,12 @@ class Assembler : public AssemblerBase {
     leal(address, FieldAddress(instance, offset_in_words_as_smi, TIMES_2, 0));
   }
 
+  void LoadFieldAddressForOffset(Register address,
+                                 Register instance,
+                                 int32_t offset) override {
+    leal(address, FieldAddress(instance, offset));
+  }
+
   static Address VMTagAddress() {
     return Address(THR, target::Thread::vm_tag_offset());
   }