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Enbale TYP_MASK support for ARM64 #103818

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merged 3 commits into from
Jun 22, 2024
Merged

Enbale TYP_MASK support for ARM64 #103818

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e713e75
Enbale TYP_MASK support for ARM64
mikabl-arm Jun 20, 2024
38e16cf
cleanup: check for a FEATURE macro instead of TARGET
mikabl-arm Jun 21, 2024
972b42f
jit format
kunalspathak Jun 21, 2024
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5 changes: 4 additions & 1 deletion src/coreclr/jit/assertionprop.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2997,6 +2997,9 @@ GenTree* Compiler::optVNBasedFoldConstExpr(BasicBlock* block, GenTree* parent, G
}
break;

#endif // TARGET_XARCH

#if defined(FEATURE_MASKED_HW_INTRINSICS)
case TYP_MASK:
{
simdmask_t value = vnStore->ConstantValue<simdmask_t>(vnCns);
Expand All @@ -3008,7 +3011,7 @@ GenTree* Compiler::optVNBasedFoldConstExpr(BasicBlock* block, GenTree* parent, G
break;
}
break;
#endif // TARGET_XARCH
#endif // FEATURE_MASKED_HW_INTRINSICS
#endif // FEATURE_SIMD

case TYP_BYREF:
Expand Down
5 changes: 4 additions & 1 deletion src/coreclr/jit/emit.cpp
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Expand Up @@ -8225,6 +8225,9 @@ CORINFO_FIELD_HANDLE emitter::emitSimd64Const(simd64_t constValue)
return emitComp->eeFindJitDataOffs(cnum);
}

#endif // TARGET_XARCH

#if defined(FEATURE_MASKED_HW_INTRINSICS)
CORINFO_FIELD_HANDLE emitter::emitSimdMaskConst(simdmask_t constValue)
{
unsigned cnsSize = 8;
Expand All @@ -8240,7 +8243,7 @@ CORINFO_FIELD_HANDLE emitter::emitSimdMaskConst(simdmask_t constValue)
UNATIVE_OFFSET cnum = emitDataConst(&constValue, cnsSize, cnsAlign, TYP_MASK);
return emitComp->eeFindJitDataOffs(cnum);
}
#endif // TARGET_XARCH
#endif // FEATURE_MASKED_HW_INTRINSICS
#endif // FEATURE_SIMD

/*****************************************************************************
Expand Down
5 changes: 4 additions & 1 deletion src/coreclr/jit/emit.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2525,8 +2525,11 @@ class emitter
#if defined(TARGET_XARCH)
CORINFO_FIELD_HANDLE emitSimd32Const(simd32_t constValue);
CORINFO_FIELD_HANDLE emitSimd64Const(simd64_t constValue);
CORINFO_FIELD_HANDLE emitSimdMaskConst(simdmask_t constValue);
#endif // TARGET_XARCH

#if defined(FEATURE_MASKED_HW_INTRINSICS)
CORINFO_FIELD_HANDLE emitSimdMaskConst(simdmask_t constValue);
#endif // FEATURE_MASKED_HW_INTRINSICS
#endif // FEATURE_SIMD
regNumber emitInsBinary(instruction ins, emitAttr attr, GenTree* dst, GenTree* src);
regNumber emitInsTernary(instruction ins, emitAttr attr, GenTree* dst, GenTree* src1, GenTree* src2);
Expand Down
9 changes: 7 additions & 2 deletions src/coreclr/jit/gentree.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3397,14 +3397,16 @@ unsigned Compiler::gtHashValue(GenTree* tree)
switch (vecCon->TypeGet())
{
#if defined(FEATURE_SIMD)
#if defined(TARGET_XARCH)
#if defined(FEATURE_MASKED_HW_INTRINSICS)
case TYP_MASK:
{
add = genTreeHashAdd(ulo32(add), vecCon->gtSimdVal.u32[1]);
add = genTreeHashAdd(ulo32(add), vecCon->gtSimdVal.u32[0]);
break;
}
#endif // FEATURE_MASKED_HW_INTRINSICS

#if defined(TARGET_XARCH)
case TYP_SIMD64:
{
add = genTreeHashAdd(ulo32(add), vecCon->gtSimdVal.u32[15]);
Expand Down Expand Up @@ -12299,12 +12301,15 @@ void Compiler::gtDispConst(GenTree* tree)
break;
}

#endif // TARGET_XARCH

#if defined(FEATURE_MASKED_HW_INTRINSICS)
case TYP_MASK:
{
printf("<0x%08x, 0x%08x>", vecCon->gtSimdVal.u32[0], vecCon->gtSimdVal.u32[1]);
break;
}
#endif // TARGET_XARCH
#endif // FEATURE_MASKED_HW_INTRINSICS

default:
{
Expand Down
24 changes: 18 additions & 6 deletions src/coreclr/jit/gentree.h
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Original file line number Diff line number Diff line change
Expand Up @@ -6657,11 +6657,14 @@ struct GenTreeVecCon : public GenTree
simd16_t gtSimd16Val;

#if defined(TARGET_XARCH)
simd32_t gtSimd32Val;
simd64_t gtSimd64Val;
simdmask_t gtSimdMaskVal;
simd32_t gtSimd32Val;
simd64_t gtSimd64Val;
#endif // TARGET_XARCH

#if defined(FEATURE_MASKED_HW_INTRINSICS)
simdmask_t gtSimdMaskVal;
#endif // FEATURE_MASKED_HW_INTRINSICS

simd_t gtSimdVal;
};

Expand Down Expand Up @@ -7084,11 +7087,14 @@ struct GenTreeVecCon : public GenTree
return gtSimd64Val.IsAllBitsSet();
}

#endif // TARGET_XARCH

#if defined(FEATURE_MASKED_HW_INTRINSICS)
case TYP_MASK:
{
return gtSimdMaskVal.IsAllBitsSet();
}
#endif // TARGET_XARCH
#endif // FEATURE_MASKED_HW_INTRINSICS
#endif // FEATURE_SIMD

default:
Expand Down Expand Up @@ -7138,11 +7144,14 @@ struct GenTreeVecCon : public GenTree
return left->gtSimd64Val == right->gtSimd64Val;
}

#endif // TARGET_XARCH

#if defined(FEATURE_MASKED_HW_INTRINSICS)
case TYP_MASK:
{
return left->gtSimdMaskVal == right->gtSimdMaskVal;
}
#endif // TARGET_XARCH
#endif // FEATURE_MASKED_HW_INTRINSICS
#endif // FEATURE_SIMD

default:
Expand Down Expand Up @@ -7187,11 +7196,14 @@ struct GenTreeVecCon : public GenTree
return gtSimd64Val.IsZero();
}

#endif // TARGET_XARCH

#if defined(FEATURE_MASKED_HW_INTRINSICS)
case TYP_MASK:
{
return gtSimdMaskVal.IsZero();
}
#endif // TARGET_XARCH
#endif // FEATURE_MASKED_HW_INTRINSICS
#endif // FEATURE_SIMD

default:
Expand Down
5 changes: 4 additions & 1 deletion src/coreclr/jit/instr.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -990,13 +990,16 @@ CodeGen::OperandDesc CodeGen::genOperandDesc(GenTree* op)
return OperandDesc(emit->emitSimd64Const(constValue));
}

#endif // TARGET_XARCH

#if defined(FEATURE_MASKED_HW_INTRINSICS)
case TYP_MASK:
{
simdmask_t constValue;
memcpy(&constValue, &op->AsVecCon()->gtSimdVal, sizeof(simdmask_t));
return OperandDesc(emit->emitSimdMaskConst(constValue));
}
#endif // TARGET_XARCH
#endif // FEATURE_MASKED_HW_INTRINSICS
#endif // FEATURE_SIMD

default:
Expand Down
4 changes: 4 additions & 0 deletions src/coreclr/jit/simd.h
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Original file line number Diff line number Diff line change
Expand Up @@ -292,7 +292,9 @@ struct simd64_t
}
};
static_assert_no_msg(sizeof(simd64_t) == 64);
#endif // TARGET_XARCH

#if defined(FEATURE_MASKED_HW_INTRINSICS)
struct simdmask_t
{
union
Expand Down Expand Up @@ -342,7 +344,9 @@ struct simdmask_t
}
};
static_assert_no_msg(sizeof(simdmask_t) == 8);
#endif // FEATURE_MASKED_HW_INTRINSICS

#if defined(TARGET_XARCH)
typedef simd64_t simd_t;
#else
typedef simd16_t simd_t;
Expand Down
46 changes: 35 additions & 11 deletions src/coreclr/jit/valuenum.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -437,8 +437,10 @@ ValueNumStore::ValueNumStore(Compiler* comp, CompAllocator alloc)
#if defined(TARGET_XARCH)
, m_simd32CnsMap(nullptr)
, m_simd64CnsMap(nullptr)
, m_simdMaskCnsMap(nullptr)
#endif // TARGET_XARCH
#if defined(FEATURE_MASKED_HW_INTRINSICS)
, m_simdMaskCnsMap(nullptr)
#endif // FEATURE_MASKED_HW_INTRINSICS
#endif // FEATURE_SIMD
, m_VNFunc0Map(nullptr)
, m_VNFunc1Map(nullptr)
Expand Down Expand Up @@ -1711,13 +1713,15 @@ ValueNumStore::Chunk::Chunk(CompAllocator alloc, ValueNum* pNextBaseVN, var_type
m_defs = new (alloc) Alloc<TYP_SIMD64>::Type[ChunkSize];
break;
}
#endif // TARGET_XARCH

#if defined(FEATURE_MASKED_HW_INTRINSICS)
case TYP_MASK:
{
m_defs = new (alloc) Alloc<TYP_MASK>::Type[ChunkSize];
break;
}
#endif // TARGET_XARCH
#endif // FEATURE_MASKED_HW_INTRINSICS
#endif // FEATURE_SIMD

default:
Expand Down Expand Up @@ -1881,12 +1885,14 @@ ValueNum ValueNumStore::VNForSimd64Con(const simd64_t& cnsVal)
{
return VnForConst(cnsVal, GetSimd64CnsMap(), TYP_SIMD64);
}
#endif // TARGET_XARCH

#if defined(FEATURE_MASKED_HW_INTRINSICS)
ValueNum ValueNumStore::VNForSimdMaskCon(const simdmask_t& cnsVal)
{
return VnForConst(cnsVal, GetSimdMaskCnsMap(), TYP_MASK);
}
#endif // TARGET_XARCH
#endif // FEATURE_MASKED_HW_INTRINSICS
#endif // FEATURE_SIMD

ValueNum ValueNumStore::VNForGenericCon(var_types typ, uint8_t* cnsVal)
Expand Down Expand Up @@ -1987,12 +1993,15 @@ ValueNum ValueNumStore::VNForGenericCon(var_types typ, uint8_t* cnsVal)
READ_VALUE(simd64_t);
return VNForSimd64Con(val);
}
#endif // TARGET_XARCH

#if defined(FEATURE_MASKED_HW_INTRINSICS)
case TYP_MASK:
{
READ_VALUE(simdmask_t);
return VNForSimdMaskCon(val);
}
#endif // TARGET_XARCH
#endif // FEATURE_MASKED_HW_INTRINSICS
#endif // FEATURE_SIMD
default:
unreached();
Expand Down Expand Up @@ -2106,12 +2115,14 @@ ValueNum ValueNumStore::VNZeroForType(var_types typ)
{
return VNForSimd64Con(simd64_t::Zero());
}
#endif // TARGET_XARCH

#if defined(FEATURE_MASKED_HW_INTRINSICS)
case TYP_MASK:
{
return VNForSimdMaskCon(simdmask_t::Zero());
}
#endif // TARGET_XARCH
#endif // FEATURE_MASKED_HW_INTRINSICS
#endif // FEATURE_SIMD

// These should be unreached.
Expand Down Expand Up @@ -2201,12 +2212,14 @@ ValueNum ValueNumStore::VNAllBitsForType(var_types typ)
{
return VNForSimd64Con(simd64_t::AllBitsSet());
}
#endif // TARGET_XARCH

#if defined(FEATURE_MASKED_HW_INTRINSICS)
case TYP_MASK:
{
return VNForSimdMaskCon(simdmask_t::AllBitsSet());
}
#endif // TARGET_XARCH
#endif // FEATURE_MASKED_HW_INTRINSICS
#endif // FEATURE_SIMD

default:
Expand Down Expand Up @@ -2319,11 +2332,14 @@ ValueNum ValueNumStore::VNBroadcastForSimdType(var_types simdType, var_types sim
return VNForSimd64Con(result);
}

#endif // TARGET_XARCH

#if defined(FEATURE_MASKED_HW_INTRINSICS)
case TYP_MASK:
{
unreached();
}
#endif // TARGET_XARCH
#endif // FEATURE_MASKED_HW_INTRINSICS

default:
{
Expand Down Expand Up @@ -2390,12 +2406,14 @@ bool ValueNumStore::VNIsVectorNaN(var_types simdType, var_types simdBaseType, Va
memcpy(&vector, &tmp, genTypeSize(simdType));
break;
}
#endif // TARGET_XARCH

#if defined(FEATURE_MASKED_HW_INTRINSICS)
case TYP_MASK:
{
unreached();
}
#endif // TARGET_XARCH
#endif // FEATURE_MASKED_HW_INTRINSICS

default:
{
Expand Down Expand Up @@ -3925,7 +3943,9 @@ simd64_t ValueNumStore::GetConstantSimd64(ValueNum argVN)

return ConstantValue<simd64_t>(argVN);
}
#endif // TARGET_XARCH

#if defined(FEATURE_MASKED_HW_INTRINSICS)
// Given a simdmask constant value number return its value as a simdmask.
//
simdmask_t ValueNumStore::GetConstantSimdMask(ValueNum argVN)
Expand All @@ -3935,7 +3955,7 @@ simdmask_t ValueNumStore::GetConstantSimdMask(ValueNum argVN)

return ConstantValue<simdmask_t>(argVN);
}
#endif // TARGET_XARCH
#endif // FEATURE_MASKED_HW_INTRINSICS
#endif // FEATURE_SIMD

// Compute the proper value number when the VNFunc has all constant arguments
Expand Down Expand Up @@ -9486,14 +9506,16 @@ void ValueNumStore::vnDump(Compiler* comp, ValueNum vn, bool isPtr)
cnsVal.u64[6], cnsVal.u64[7]);
break;
}
#endif // TARGET_XARCH

#if defined(FEATURE_MASKED_HW_INTRINSICS)
case TYP_MASK:
{
simdmask_t cnsVal = GetConstantSimdMask(vn);
printf("SimdMaskCns[0x%08x, 0x%08x]", cnsVal.u32[0], cnsVal.u32[1]);
break;
}
#endif // TARGET_XARCH
#endif // FEATURE_MASKED_HW_INTRINSICS
#endif // FEATURE_SIMD

// These should be unreached.
Expand Down Expand Up @@ -10934,7 +10956,9 @@ void Compiler::fgValueNumberTreeConst(GenTree* tree)
tree->gtVNPair.SetBoth(vnStore->VNForSimd64Con(simd64Val));
break;
}
#endif // TARGET_XARCH

#if defined(FEATURE_MASKED_HW_INTRINSICS)
case TYP_MASK:
{
simdmask_t simdmaskVal;
Expand All @@ -10943,7 +10967,7 @@ void Compiler::fgValueNumberTreeConst(GenTree* tree)
tree->gtVNPair.SetBoth(vnStore->VNForSimdMaskCon(simdmaskVal));
break;
}
#endif // TARGET_XARCH
#endif // FEATURE_MASKED_HW_INTRINSICS
#endif // FEATURE_SIMD

case TYP_FLOAT:
Expand Down
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