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[RISC-V] PerfScore #113011
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[RISC-V] PerfScore #113011
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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch |
RISC-V Release-CLR-VF2: 9464 / 9540 (99.20%)
Release-CLR-VF2.md, Release-CLR-VF2.xml, testclr_output.tar.gz Build information and commandsGIT: RISC-V Release-CLR-QEMU: 9464 / 9540 (99.20%)
Release-CLR-QEMU.md, Release-CLR-QEMU.xml, testclr_output.tar.gz Build information and commandsGIT: RISC-V Release-FX-QEMU: 638451 / 661414 (96.53%)
Release-FX-QEMU.md, Release-FX-QEMU.xml, testfx_output.tar.gz Build information and commandsGIT: RISC-V Release-FX-VF2: 483327 / 511708 (94.45%)
Build information and commandsGIT: |
case MajorOpcode::System: | ||
{ | ||
code_t funct3 = (code >> 12) & 0b111; | ||
return (funct3 != 0); // CSR read/writes | ||
} |
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Bugfix, was missing from #110390
// clang-format off | ||
// inst[4:2] 000, 001, 010, 011, 100, 101, 110, 111 (>32Bit) | ||
/* inst[6:5] */ | ||
/* 00 */ Load, LoadFp, Custom0, MiscMem, OpImm, Auipc, OpImm32, Encoding48Bit1, | ||
/* 01 */ Store, StoreFp, Custom1, Amo, Op, Lui, Op32, Encoding64Bit, | ||
/* 11 */ MAdd, MSub, NmSub, NmAdd, OpFp, OpV, Custom2Rv128, Encoding48Bit2, | ||
/* 11 */ Branch, Jalr, Reserved, Jal, System, OpVe, Custom3Rv128, Encoding80Bit, | ||
// clang-format on |
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Format suspended for easier vetting against the spec.
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Format suspended for easier vetting against the spec.
This link could be part of the code comment for future readers. :)
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The ISA is still expanding, I didn't include a link in case it e.g. moves between files. I put the title in enum comment so it can be ctrl+f'ed.
RISC-V Release-CLR-VF2: 9464 / 9540 (99.20%)
Release-CLR-VF2.md, Release-CLR-VF2.xml, testclr_output.tar.gz Build information and commandsGIT: RISC-V Release-CLR-QEMU: 9464 / 9540 (99.20%)
Release-CLR-QEMU.md, Release-CLR-QEMU.xml, testclr_output.tar.gz Build information and commandsGIT: RISC-V Release-FX-VF2: 627350 / 660806 (94.94%)
Build information and commandsGIT: RISC-V Release-FX-QEMU: 626158 / 654510 (95.67%)
Release-FX-QEMU.md, Release-FX-QEMU.xml, testfx_output.tar.gz Build information and commandsGIT: |
RISC-V Release-CLR-VF2: 9464 / 9540 (99.20%)
Release-CLR-VF2.md, Release-CLR-VF2.xml, testclr_output.tar.gz Build information and commandsGIT: RISC-V Release-CLR-QEMU: 9464 / 9540 (99.20%)
Release-CLR-QEMU.md, Release-CLR-QEMU.xml, testclr_output.tar.gz Build information and commandsGIT: RISC-V Release-FX-QEMU: 635674 / 668114 (95.14%)
Release-FX-QEMU.md, Release-FX-QEMU.xml, testfx_output.tar.gz Build information and commandsGIT: RISC-V Release-FX-VF2: 624418 / 652231 (95.74%)
Build information and commandsGIT: |
Based on the SiFive U74 core (VisionFive 2). Instruction characteristics in the spec are often implied or lacking but it's something to start with.
Part of #84834, cc @dotnet/samsung