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[RyuJIT] Add "rorx" instruction (BMI2) and emit it instead of "rol" when possible #41772

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merged 15 commits into from
Sep 29, 2020
Merged

[RyuJIT] Add "rorx" instruction (BMI2) and emit it instead of "rol" when possible #41772

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562a10c
Use rorx instead of rol when possible
EgorBo Sep 2, 2020
928c55d
check for BMI2 availability
EgorBo Sep 3, 2020
ab495fc
Update codegenxarch.cpp
EgorBo Sep 3, 2020
ddb3382
Update codegenxarch.cpp
EgorBo Sep 3, 2020
462719c
Merge branch 'master' of github.com:dotnet/runtime into add-rorx-inst…
EgorBo Sep 3, 2020
b85c87b
formatting
EgorBo Sep 3, 2020
d808b86
Merge branch 'master' of github.com:dotnet/runtime into add-rorx-inst…
EgorBo Sep 4, 2020
739007b
handle GT_ROR
EgorBo Sep 4, 2020
c5933e9
clean up
EgorBo Sep 4, 2020
609af9e
Don't emit rorx when targetReg == operandReg
EgorBo Sep 5, 2020
1b3e055
Merge branch 'master' of github.com:dotnet/runtime into add-rorx-inst…
EgorBo Sep 9, 2020
5a36432
emit rorx only for long integers
EgorBo Sep 9, 2020
da9d166
wrap with TARGET_64BIT
EgorBo Sep 9, 2020
7cbb1ce
clean up
EgorBo Sep 9, 2020
9e9b1cb
clean up
EgorBo Sep 9, 2020
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30 changes: 21 additions & 9 deletions src/coreclr/src/jit/codegenxarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4067,10 +4067,11 @@ void CodeGen::genCodeForShift(GenTree* tree)

if (shiftBy->isContainedIntOrIImmed())
{
emitAttr size = emitTypeSize(tree);

// Optimize "X<<1" to "lea [reg+reg]" or "add reg, reg"
if (tree->OperIs(GT_LSH) && !tree->gtOverflowEx() && !tree->gtSetFlags() && shiftBy->IsIntegralConst(1))
{
emitAttr size = emitTypeSize(tree);
if (tree->GetRegNum() == operandReg)
{
GetEmitter()->emitIns_R_R(INS_add, size, tree->GetRegNum(), operandReg);
Expand All @@ -4082,16 +4083,27 @@ void CodeGen::genCodeForShift(GenTree* tree)
}
else
{
// First, move the operand to the destination register and
// later on perform the shift in-place.
// (LSRA will try to avoid this situation through preferencing.)
if (tree->GetRegNum() != operandReg)
int typeWidth = genTypeSize(genActualType(targetType)) * 8;
int shiftByValue = (int)shiftBy->AsIntConCommon()->IconValue();
if (compiler->compOpportunisticallyDependsOn(InstructionSet_BMI2) && tree->OperIs(GT_ROL) && (shiftByValue > 0) &&
(shiftByValue < typeWidth))
{
inst_RV_RV(INS_mov, tree->GetRegNum(), operandReg, targetType);
}
assert((typeWidth == 32) || (typeWidth == 64));

int shiftByValue = (int)shiftBy->AsIntConCommon()->IconValue();
inst_RV_SH(ins, emitTypeSize(tree), tree->GetRegNum(), shiftByValue);
int reversedValue = typeWidth - shiftByValue;
GetEmitter()->emitIns_R_R_I(INS_rorx, size, tree->GetRegNum(), operandReg, reversedValue);
}
else
{
// First, move the operand to the destination register and
// later on perform the shift in-place.
// (LSRA will try to avoid this situation through preferencing.)
if (tree->GetRegNum() != operandReg)
{
inst_RV_RV(INS_mov, tree->GetRegNum(), operandReg, targetType);
}
inst_RV_SH(ins, size, tree->GetRegNum(), shiftByValue);
}
}
}
else
Expand Down
4 changes: 4 additions & 0 deletions src/coreclr/src/jit/emitxarch.cpp
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Expand Up @@ -524,6 +524,7 @@ bool TakesRexWPrefix(instruction ins, emitAttr attr)
case INS_mulx:
case INS_pdep:
case INS_pext:
case INS_rorx:
return true;
default:
return false;
Expand Down Expand Up @@ -758,6 +759,7 @@ unsigned emitter::emitOutputRexOrVexPrefixIfNeeded(instruction ins, BYTE* dst, c
{
switch (ins)
{
case INS_rorx:
case INS_pdep:
case INS_mulx:
{
Expand Down Expand Up @@ -1242,6 +1244,7 @@ bool emitter::emitInsCanOnlyWriteSSE2OrAVXReg(instrDesc* id)
case INS_pextrq:
case INS_pextrw:
case INS_pextrw_sse41:
case INS_rorx:
{
// These SSE instructions write to a general purpose integer register.
return false;
Expand Down Expand Up @@ -14938,6 +14941,7 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
case INS_tzcnt:
case INS_popcnt:
case INS_crc32:
case INS_rorx:
case INS_pdep:
case INS_pext:
case INS_addsubps:
Expand Down
1 change: 1 addition & 0 deletions src/coreclr/src/jit/instrsxarch.h
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Expand Up @@ -594,6 +594,7 @@ INST3(blsr, "blsr", IUM_WR, BAD_CODE, BAD_CODE,
INST3(bextr, "bextr", IUM_WR, BAD_CODE, BAD_CODE, SSE38(0xF7), INS_Flags_IsDstDstSrcAVXInstruction) // Bit Field Extract

// BMI2
INST3(rorx, "rorx", IUM_WR, BAD_CODE, BAD_CODE, SSE3A(0xF0), INS_FLAGS_None)
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It would be good to double-check that neither the IsDstDstSrcAVXInstruction nor IsDstSrcSrcAVXInstruction flags apply. The instruction looks to be a dst, src, imm operand in this case and so it shouldn't be flagged as RMW and should go down the right encoding paths in emit.

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@EgorBo EgorBo Sep 3, 2020 •
edited
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tried both of these flags and observed SEH exceptions on start 😞 with INS_FLAGS_None works like a charm.

INST3(pdep, "pdep", IUM_WR, BAD_CODE, BAD_CODE, SSE38(0xF5), INS_Flags_IsDstDstSrcAVXInstruction) // Parallel Bits Deposit
INST3(pext, "pext", IUM_WR, BAD_CODE, BAD_CODE, SSE38(0xF5), INS_Flags_IsDstDstSrcAVXInstruction) // Parallel Bits Extract
INST3(bzhi, "bzhi", IUM_WR, BAD_CODE, BAD_CODE, SSE38(0xF5), INS_Flags_IsDstDstSrcAVXInstruction) // Zero High Bits Starting with Specified Bit Position
Expand Down