[RISC-V] coreclr-vm and other directories in coreclr

src/coreclr/clrdefinitions.cmake

@@ -197,12 +197,12 @@ if (CLR_CMAKE_TARGET_ARCH_AMD64)
   add_definitions(-DUNIX_AMD64_ABI_ITF)
 endif (CLR_CMAKE_TARGET_ARCH_AMD64)
 add_definitions(-DFEATURE_USE_ASM_GC_WRITE_BARRIERS)
-if(CLR_CMAKE_TARGET_ARCH_AMD64 OR CLR_CMAKE_TARGET_ARCH_ARM64 OR CLR_CMAKE_TARGET_ARCH_LOONGARCH64)
+if(CLR_CMAKE_TARGET_ARCH_AMD64 OR CLR_CMAKE_TARGET_ARCH_ARM64 OR CLR_CMAKE_TARGET_ARCH_LOONGARCH64 OR CLR_CMAKE_TARGET_ARCH_RISCV64)
   add_definitions(-DFEATURE_USE_SOFTWARE_WRITE_WATCH_FOR_GC_HEAP)
-endif(CLR_CMAKE_TARGET_ARCH_AMD64 OR CLR_CMAKE_TARGET_ARCH_ARM64 OR CLR_CMAKE_TARGET_ARCH_LOONGARCH64)
-if(CLR_CMAKE_TARGET_ARCH_AMD64 OR CLR_CMAKE_TARGET_ARCH_ARM64 OR CLR_CMAKE_TARGET_ARCH_LOONGARCH64)
+endif(CLR_CMAKE_TARGET_ARCH_AMD64 OR CLR_CMAKE_TARGET_ARCH_ARM64 OR CLR_CMAKE_TARGET_ARCH_LOONGARCH64 OR CLR_CMAKE_TARGET_ARCH_RISCV64)
+if(CLR_CMAKE_TARGET_ARCH_AMD64 OR CLR_CMAKE_TARGET_ARCH_ARM64 OR CLR_CMAKE_TARGET_ARCH_LOONGARCH64 OR CLR_CMAKE_TARGET_ARCH_RISCV64)
   add_definitions(-DFEATURE_MANUALLY_MANAGED_CARD_BUNDLES)
-endif(CLR_CMAKE_TARGET_ARCH_AMD64 OR CLR_CMAKE_TARGET_ARCH_ARM64 OR CLR_CMAKE_TARGET_ARCH_LOONGARCH64)
+endif(CLR_CMAKE_TARGET_ARCH_AMD64 OR CLR_CMAKE_TARGET_ARCH_ARM64 OR CLR_CMAKE_TARGET_ARCH_LOONGARCH64 OR CLR_CMAKE_TARGET_ARCH_RISCV64)
 
 if(NOT CLR_CMAKE_TARGET_UNIX)
     add_definitions(-DFEATURE_WIN32_REGISTRY)
@@ -275,6 +275,10 @@ function(set_target_definitions_to_custom_os_and_arch)
     target_compile_definitions(${TARGETDETAILS_TARGET} PRIVATE FEATURE_MULTIREG_RETURN)
   elseif((TARGETDETAILS_ARCH STREQUAL "arm") OR (TARGETDETAILS_ARCH STREQUAL "armel"))
     target_compile_definitions(${TARGETDETAILS_TARGET} PRIVATE TARGET_ARM)
+  elseif((TARGETDETAILS_ARCH STREQUAL "riscv64"))
+    target_compile_definitions(${TARGETDETAILS_TARGET} PRIVATE TARGET_64BIT)
+    target_compile_definitions(${TARGETDETAILS_TARGET} PRIVATE TARGET_RISCV64)
+    target_compile_definitions(${TARGETDETAILS_TARGET} PRIVATE FEATURE_MULTIREG_RETURN)
   endif()
 
   if (TARGETDETAILS_ARCH STREQUAL "armel")

src/coreclr/dlls/mscordac/CMakeLists.txt

@@ -49,6 +49,8 @@ else(CLR_CMAKE_HOST_WIN32)
 
         if (CLR_CMAKE_HOST_ARCH_ARM OR CLR_CMAKE_HOST_ARCH_ARM64 OR CLR_CMAKE_HOST_ARCH_LOONGARCH64)
             set(JUMP_INSTRUCTION b)
+        elseif (CLR_CMAKE_HOST_ARCH_RISCV64)
+            set(JUMP_INSTRUCTION tail)
         else()
             set(JUMP_INSTRUCTION jmp)
         endif()

src/coreclr/gc/env/gcenv.base.h

@@ -226,6 +226,11 @@ typedef DWORD (WINAPI *PTHREAD_START_ROUTINE)(void* lpThreadParameter);
  #define MemoryBarrier __sync_synchronize
 #endif // __loongarch64
 
+#ifdef __riscv
+ #define YieldProcessor() asm volatile( ".word 0x0100000f");
+ #define MemoryBarrier __sync_synchronize
+#endif // __riscv
+
 #endif // _MSC_VER
 
 #ifdef _MSC_VER

src/coreclr/gc/env/volatile.h

@@ -66,8 +66,8 @@
 #error The Volatile type is currently only defined for Visual C++ and GNU C++
 #endif
 
-#if defined(__GNUC__) && !defined(HOST_X86) && !defined(HOST_AMD64) && !defined(HOST_ARM) && !defined(HOST_ARM64) && !defined(HOST_LOONGARCH64) && !defined(HOST_WASM)
-#error The Volatile type is currently only defined for GCC when targeting x86, AMD64, ARM, ARM64, LOONGARCH64 or Wasm
+#if defined(__GNUC__) && !defined(HOST_X86) && !defined(HOST_AMD64) && !defined(HOST_ARM) && !defined(HOST_ARM64) && !defined(HOST_LOONGARCH64) && !defined(HOST_WASM) && !defined(HOST_RISCV64)
+#error The Volatile type is currently only defined for GCC when targeting x86, AMD64, ARM, ARM64, LOONGARCH64, Wasm, RISCV64
 #endif
 
 #if defined(__GNUC__)
@@ -76,6 +76,8 @@
 #define VOLATILE_MEMORY_BARRIER() asm volatile ("dmb ish" : : : "memory")
 #elif defined(HOST_LOONGARCH64)
 #define VOLATILE_MEMORY_BARRIER() asm volatile ("dbar 0 " : : : "memory")
+#elif defined(HOST_RISCV64)
+#define VOLATILE_MEMORY_BARRIER() asm volatile ("fence rw,rw" : : : "memory")
 #else
 //
 // For GCC, we prevent reordering by the compiler by inserting the following after a volatile

src/coreclr/gcdump/gcdumpnonx86.cpp

@@ -72,6 +72,9 @@ PCSTR GetRegName (UINT32 regnum)
 #elif defined(TARGET_LOONGARCH64)
     assert(!"unimplemented on LOONGARCH yet");
     return "???";
+#elif defined(TARGET_RISCV64)
+    assert(!"unimplemented on RISCV64 yet");
+    return "???";
 #endif
 }
 

src/coreclr/gcinfo/CMakeLists.txt

@@ -79,6 +79,10 @@ if (CLR_CMAKE_TARGET_ARCH_LOONGARCH64)
   create_gcinfo_lib(TARGET gcinfo_unix_loongarch64 OS unix ARCH loongarch64)
 endif (CLR_CMAKE_TARGET_ARCH_LOONGARCH64)
 
+if (CLR_CMAKE_TARGET_ARCH_RISCV64)
+  create_gcinfo_lib(TARGET gcinfo_unix_riscv64 OS unix ARCH riscv64)
+endif (CLR_CMAKE_TARGET_ARCH_RISCV64)
+
 create_gcinfo_lib(TARGET gcinfo_universal_arm OS universal ARCH arm)
 create_gcinfo_lib(TARGET gcinfo_win_x86 OS win ARCH x86)
 

src/coreclr/gcinfo/gcinfodumper.cpp

@@ -224,6 +224,45 @@ BOOL GcInfoDumper::ReportPointerRecord (
         REG(ra, Ra),
         { offsetof(T_CONTEXT, Sp) },
 #undef REG
+#elif defined(TARGET_RISCV64)
+#undef REG
+#define REG(reg, field) { offsetof(Riscv64VolatileContextPointer, field) }
+        REG(zero, R0),
+        REG(a0, A0),
+        REG(a1, A1),
+        REG(a2, A2),
+        REG(a3, A3),
+        REG(a4, A4),
+        REG(a5, A5),
+        REG(a6, A6),
+        REG(a7, A7),
+        REG(t0, T0),
+        REG(t1, T1),
+        REG(t2, T2),
+        REG(t3, T3),
+        REG(t4, T4),
+        REG(t5, T5),
+        REG(t6, T6),
+#undef REG
+#define REG(reg, field) { offsetof(T_KNONVOLATILE_CONTEXT_POINTERS, field) }
+        REG(s1, S1),
+        REG(s2, S2),
+        REG(s3, S3),
+        REG(s4, S4),
+        REG(s5, S5),
+        REG(s6, S6),
+        REG(s7, S7),
+        REG(s8, S8),
+        REG(s9, S9),
+        REG(s10, S10),
+        REG(s11, S11),
+        REG(ra, Ra),
+        REG(gp, Gp),
+        REG(tp, Tp),
+        REG(fp, Fp),
+        { offsetof(T_CONTEXT, Sp) },
+#undef REG
+
 #else
 PORTABILITY_ASSERT("GcInfoDumper::ReportPointerRecord is not implemented on this platform.")
 #endif
@@ -248,6 +287,9 @@ PORTABILITY_ASSERT("GcInfoDumper::ReportPointerRecord is not implemented on this
 #elif defined(TARGET_LOONGARCH64)
     assert(!"unimplemented on LOONGARCH yet");
     iSPRegister = 0;
+#elif defined(TARGET_RISCV64)
+    assert(!"unimplemented on RISCV64 yet");
+    iSPRegister = 0;
 #endif
 
 #if defined(TARGET_ARM) || defined(TARGET_ARM64)
@@ -660,8 +702,11 @@ GcInfoDumper::EnumerateStateChangesResults GcInfoDumper::EnumerateStateChanges (
 #elif defined(TARGET_LOONGARCH64)
 #pragma message("Unimplemented for LOONGARCH64 yet.")
     assert(!"unimplemented on LOONGARCH yet");
+#elif defined(TARGET_RISCV64)
+#pragma message("Unimplemented for RISCV64 yet.")
+    assert(!"unimplemented on RISCV64 yet");
 #else
-PORTABILITY_ASSERT("GcInfoDumper::EnumerateStateChanges is not implemented on this platform.")
+PORTABILITY_ASSERT("GcInfoDumper::EnumerateStateChanges is not implemented on this platform.");
 #endif
 
 #undef FILL_REGS

src/coreclr/gcinfo/gcinfoencoder.cpp

@@ -479,7 +479,7 @@ GcInfoEncoder::GcInfoEncoder(
     m_ReversePInvokeFrameSlot = NO_REVERSE_PINVOKE_FRAME;
 #ifdef TARGET_AMD64
     m_WantsReportOnlyLeaf = false;
-#elif defined(TARGET_ARM) || defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64)
+#elif defined(TARGET_ARM) || defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
     m_HasTailCalls = false;
 #endif // TARGET_AMD64
     m_IsVarArg = false;
@@ -729,6 +729,8 @@ void GcInfoEncoder::SetStackBaseRegister( UINT32 regNum )
     _ASSERTE( m_StackBaseRegister == NO_STACK_BASE_REGISTER || m_StackBaseRegister == regNum );
 #if defined(TARGET_LOONGARCH64)
     assert(regNum == 3 || 22 == regNum);
+#elif defined(TARGET_RISCV64)
+    assert(regNum == 2 || 8 == regNum);
 #endif
     m_StackBaseRegister = regNum;
 }
@@ -752,7 +754,7 @@ void GcInfoEncoder::SetWantsReportOnlyLeaf()
 {
     m_WantsReportOnlyLeaf = true;
 }
-#elif defined(TARGET_ARM) || defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64)
+#elif defined(TARGET_ARM) || defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
 void GcInfoEncoder::SetHasTailCalls()
 {
     m_HasTailCalls = true;
@@ -1011,7 +1013,7 @@ void GcInfoEncoder::Build()
         (m_SizeOfEditAndContinuePreservedArea == NO_SIZE_OF_EDIT_AND_CONTINUE_PRESERVED_AREA) &&
 #ifdef TARGET_AMD64
         !m_WantsReportOnlyLeaf &&
-#elif defined(TARGET_ARM) || defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64)
+#elif defined(TARGET_ARM) || defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
         !m_HasTailCalls &&
 #endif // TARGET_AMD64
         !IsStructReturnKind(m_ReturnKind);
@@ -1024,6 +1026,8 @@ void GcInfoEncoder::Build()
         GCINFO_WRITE(m_Info1, 0, 1, FlagsSize); // Slim encoding
 #if defined(TARGET_LOONGARCH64)
         assert(m_StackBaseRegister == 22 || 3 == m_StackBaseRegister);
+#elif defined(TARGET_RISCV64)
+        assert(m_StackBaseRegister == 8 || 2 == m_StackBaseRegister);
 #endif
         GCINFO_WRITE(m_Info1, (m_StackBaseRegister == NO_STACK_BASE_REGISTER) ? 0 : 1, 1, FlagsSize);
 
@@ -1039,11 +1043,13 @@ void GcInfoEncoder::Build()
         GCINFO_WRITE(m_Info1, m_contextParamType, 2, FlagsSize);
 #if defined(TARGET_LOONGARCH64)
         assert(m_StackBaseRegister == 22 || 3 == m_StackBaseRegister);
+#elif defined(TARGET_RISCV64)
+        assert(m_StackBaseRegister == 8 || 2 == m_StackBaseRegister);
 #endif
         GCINFO_WRITE(m_Info1, ((m_StackBaseRegister != NO_STACK_BASE_REGISTER) ? 1 : 0), 1, FlagsSize);
 #ifdef TARGET_AMD64
         GCINFO_WRITE(m_Info1, (m_WantsReportOnlyLeaf ? 1 : 0), 1, FlagsSize);
-#elif defined(TARGET_ARM) || defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64)
+#elif defined(TARGET_ARM) || defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
         GCINFO_WRITE(m_Info1, (m_HasTailCalls ? 1 : 0), 1, FlagsSize);
 #endif // TARGET_AMD64
         GCINFO_WRITE(m_Info1, ((m_SizeOfEditAndContinuePreservedArea != NO_SIZE_OF_EDIT_AND_CONTINUE_PRESERVED_AREA) ? 1 : 0), 1, FlagsSize);
@@ -1129,6 +1135,8 @@ void GcInfoEncoder::Build()
     {
 #if defined(TARGET_LOONGARCH64)
         assert(m_StackBaseRegister == 22 || 3 == m_StackBaseRegister);
+#elif defined(TARGET_RISCV64)
+        assert(m_StackBaseRegister == 8 || 2 == m_StackBaseRegister);
 #endif
         GCINFO_WRITE_VARL_U(m_Info1, NORMALIZE_STACK_BASE_REGISTER(m_StackBaseRegister), STACK_BASE_REGISTER_ENCBASE, StackBaseSize);
     }

src/coreclr/inc/clrconfigvalues.h

@@ -298,7 +298,13 @@ CONFIG_DWORD_INFO(INTERNAL_JitDebuggable, W("JitDebuggable"), 0, "")
 #define INTERNAL_JitEnableNoWayAssert_Default 1
 #endif
 RETAIL_CONFIG_DWORD_INFO(INTERNAL_JitEnableNoWayAssert, W("JitEnableNoWayAssert"), INTERNAL_JitEnableNoWayAssert_Default, "")
+
+#if defined(TARGET_RISCV64)
+// TODO-RISCV64-CQ: In RISCV64, currently jitc always generates JitFramed codes.
+RETAIL_CONFIG_DWORD_INFO(UNSUPPORTED_JitFramed, W("JitFramed"), 1, "Forces EBP frames")
+#else
 RETAIL_CONFIG_DWORD_INFO(UNSUPPORTED_JitFramed, W("JitFramed"), 0, "Forces EBP frames")
+#endif // TARGET_RISCV64
 CONFIG_DWORD_INFO(INTERNAL_JitThrowOnAssertionFailure, W("JitThrowOnAssertionFailure"), 0, "Throw managed exception on assertion failures during JIT instead of failfast")
 CONFIG_DWORD_INFO(INTERNAL_JitGCStress, W("JitGCStress"), 0, "GC stress mode for jit")
 CONFIG_DWORD_INFO(INTERNAL_JitHeartbeat, W("JitHeartbeat"), 0, "")
@@ -742,12 +748,13 @@ RETAIL_CONFIG_DWORD_INFO(INTERNAL_GDBJitEmitDebugFrame, W("GDBJitEmitDebugFrame"
 //
 // Hardware Intrinsic ISAs; keep in sync with jitconfigvalues.h
 //
-#if defined(TARGET_LOONGARCH64)
+#if defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
 //TODO: should implement LoongArch64's features.
+//TODO-RISCV64-CQ: should implement RISCV64's features.
 RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableHWIntrinsic,  W("EnableHWIntrinsic"),  0, "Allows Base+ hardware intrinsics to be disabled")
 #else
 RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableHWIntrinsic,  W("EnableHWIntrinsic"),  1, "Allows Base+ hardware intrinsics to be disabled")
-#endif // defined(TARGET_LOONGARCH64)
+#endif // defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
 
 #if defined(TARGET_AMD64) || defined(TARGET_X86)
 RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAES,          W("EnableAES"),          1, "Allows AES+ hardware intrinsics to be disabled")

src/coreclr/inc/clrnt.h

@@ -1084,4 +1084,61 @@ RtlVirtualUnwind(
 
 #endif // TARGET_LOONGARCH64
 
+#ifdef TARGET_RISCV64
+#include "daccess.h"
+
+#define UNW_FLAG_NHANDLER               0x0             /* any handler */
+#define UNW_FLAG_EHANDLER               0x1             /* filter handler */
+#define UNW_FLAG_UHANDLER               0x2             /* unwind handler */
+
+// This function returns the RVA of the end of the function (exclusive, so one byte after the actual end)
+// using the unwind info on ARM64. (see ExternalAPIs\Win9CoreSystem\inc\winnt.h)
+FORCEINLINE
+ULONG64
+RtlpGetFunctionEndAddress (
+    _In_ PT_RUNTIME_FUNCTION FunctionEntry,
+    _In_ ULONG64 ImageBase
+    )
+{
+    ULONG64 FunctionLength;
+
+    FunctionLength = FunctionEntry->UnwindData;
+    if ((FunctionLength & 3) != 0) {
+        FunctionLength = (FunctionLength >> 2) & 0x7ff;
+    } else {
+        memcpy(&FunctionLength, (void*)(ImageBase + FunctionLength), sizeof(UINT32));
+        FunctionLength &= 0x3ffff;
+    }
+
+    return FunctionEntry->BeginAddress + 4 * FunctionLength;
+}
+
+#define RUNTIME_FUNCTION__BeginAddress(FunctionEntry)               ((FunctionEntry)->BeginAddress)
+#define RUNTIME_FUNCTION__SetBeginAddress(FunctionEntry,address)    ((FunctionEntry)->BeginAddress = (address))
+
+#define RUNTIME_FUNCTION__EndAddress(FunctionEntry, ImageBase)      (RtlpGetFunctionEndAddress(FunctionEntry, (ULONG64)(ImageBase)))
+
+#define RUNTIME_FUNCTION__SetUnwindInfoAddress(prf,address)         do { (prf)->UnwindData = (address); } while (0)
+
+typedef struct _UNWIND_INFO {
+    // dummy
+} UNWIND_INFO, *PUNWIND_INFO;
+
+EXTERN_C
+NTSYSAPI
+PEXCEPTION_ROUTINE
+NTAPI
+RtlVirtualUnwind(
+    IN ULONG HandlerType,
+    IN ULONG64 ImageBase,
+    IN ULONG64 ControlPc,
+    IN PRUNTIME_FUNCTION FunctionEntry,
+    IN OUT PCONTEXT ContextRecord,
+    OUT PVOID *HandlerData,
+    OUT PULONG64 EstablisherFrame,
+    IN OUT PKNONVOLATILE_CONTEXT_POINTERS ContextPointers OPTIONAL
+    );
+
+#endif // TARGET_RISCV64
+
 #endif  // CLRNT_H_

src/coreclr/inc/cordebuginfo.h

@@ -179,6 +179,40 @@ class ICorDebugInfo
         REGNUM_S7,
         REGNUM_S8,
         REGNUM_PC,
+#elif TARGET_RISCV64
+        REGNUM_R0,
+        REGNUM_RA,
+        REGNUM_SP,
+        REGNUM_GP,
+        REGNUM_TP,
+        REGNUM_T0,
+        REGNUM_T1,
+        REGNUM_T2,
+        REGNUM_FP,
+        REGNUM_S1,
+        REGNUM_A0,
+        REGNUM_A1,
+        REGNUM_A2,
+        REGNUM_A3,
+        REGNUM_A4,
+        REGNUM_A5,
+        REGNUM_A6,
+        REGNUM_A7,
+        REGNUM_S2,
+        REGNUM_S3,
+        REGNUM_S4,
+        REGNUM_S5,
+        REGNUM_S6,
+        REGNUM_S7,
+        REGNUM_S8,
+        REGNUM_S9,
+        REGNUM_S10,
+        REGNUM_S11,
+        REGNUM_T3,
+        REGNUM_T4,
+        REGNUM_T5,
+        REGNUM_T6,
+        REGNUM_PC,
 #else
         PORTABILITY_WARNING("Register numbers not defined on this platform")
 #endif
@@ -197,6 +231,8 @@ class ICorDebugInfo
         //Nothing to do here. FP is already alloted.
 #elif TARGET_LOONGARCH64
         //Nothing to do here. FP is already alloted.
+#elif TARGET_RISCV64
+        //Nothing to do here. FP is already alloted.
 #else
         // RegNum values should be properly defined for this platform
         REGNUM_FP = 0,