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JIT: ARM64 SVE format encodings, SVE_JD_4A to SVE_JN_3B #97129

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merged 18 commits into from
Jan 23, 2024
Merged

JIT: ARM64 SVE format encodings, SVE_JD_4A to SVE_JN_3B #97129

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8abc033
Added SVE_JD_4A format
TIHan Jan 17, 2024
3bf2e56
Added SVE_JD_4B format
TIHan Jan 17, 2024
89e5b82
Added SVE_JJ_4A format, added more formats but they are commented out…
TIHan Jan 18, 2024
e4f2708
Added SVE_JJ_4A_B format
TIHan Jan 18, 2024
258ed98
Revert minor change
TIHan Jan 18, 2024
32828ba
Minor cleanup
TIHan Jan 18, 2024
251404c
Cleanup. Fixed a few formats. Introduced new INS_OPTS_SCALABLE option…
TIHan Jan 18, 2024
9504bae
Added SVE_JJ_4A_C format
TIHan Jan 18, 2024
2092b95
Added SVE_JJ_4A_D format
TIHan Jan 18, 2024
36b9edb
Added SVE_JK_4A and SVE_JK_4A_B formats
TIHan Jan 18, 2024
5463ca3
Added SVE_JN_3A format
TIHan Jan 18, 2024
97b1bc0
Added SVE_JN_3B format
TIHan Jan 19, 2024
4f39393
Some comments
TIHan Jan 19, 2024
e34b1c0
Merged
TIHan Jan 19, 2024
6be93fe
Feedback
TIHan Jan 22, 2024
bb6dbf5
Feedback
TIHan Jan 22, 2024
bb52630
fix build
TIHan Jan 22, 2024
35bbf18
Formatting
TIHan Jan 22, 2024
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80 changes: 80 additions & 0 deletions src/coreclr/jit/codegenarm64test.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5811,6 +5811,86 @@ void CodeGen::genArm64EmitterUnitTestsSve()
theEmitter->emitIns_R_R_R_I(INS_sve_st4w, EA_SCALABLE, REG_V31, REG_P1, REG_R5, 28,
INS_OPTS_SCALABLE_S); // ST4W {<Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <Pg>, [<Xn|SP>{,
// #<imm>, MUL VL}]

// IF_SVE_JD_4A
theEmitter->emitIns_R_R_R_R(INS_sve_st1b, EA_SCALABLE, REG_V4, REG_P1, REG_R2, REG_R0,
INS_OPTS_SCALABLE_B); // ST1B {<Zt>.<T>}, <Pg>, [<Xn|SP>, <Xm>]
theEmitter->emitIns_R_R_R_R(INS_sve_st1b, EA_SCALABLE, REG_V4, REG_P5, REG_R6, REG_R2,
INS_OPTS_SCALABLE_H); // ST1B {<Zt>.<T>}, <Pg>, [<Xn|SP>, <Xm>]
theEmitter->emitIns_R_R_R_R(INS_sve_st1b, EA_SCALABLE, REG_V6, REG_P5, REG_R7, REG_R4,
INS_OPTS_SCALABLE_S); // ST1B {<Zt>.<T>}, <Pg>, [<Xn|SP>, <Xm>]
theEmitter->emitIns_R_R_R_R(INS_sve_st1b, EA_SCALABLE, REG_V4, REG_P0, REG_R1, REG_R2,
INS_OPTS_SCALABLE_D); // ST1B {<Zt>.<T>}, <Pg>, [<Xn|SP>, <Xm>]
theEmitter->emitIns_R_R_R_R(INS_sve_st1h, EA_SCALABLE, REG_V5, REG_P6, REG_R1, REG_R2, INS_OPTS_SCALABLE_H,
INS_SCALABLE_OPTS_LSL_N); // ST1H {<Zt>.<T>}, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
theEmitter->emitIns_R_R_R_R(INS_sve_st1h, EA_SCALABLE, REG_V1, REG_P2, REG_R3, REG_R4, INS_OPTS_SCALABLE_S,
INS_SCALABLE_OPTS_LSL_N); // ST1H {<Zt>.<T>}, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
theEmitter->emitIns_R_R_R_R(INS_sve_st1h, EA_SCALABLE, REG_V3, REG_P2, REG_R4, REG_R0, INS_OPTS_SCALABLE_D,
INS_SCALABLE_OPTS_LSL_N); // ST1H {<Zt>.<T>}, <Pg>, [<Xn|SP>, <Xm>, LSL #1]

// IF_SVE_JD_4B
theEmitter->emitIns_R_R_R_R(INS_sve_st1w, EA_SCALABLE, REG_V0, REG_P1, REG_R2, REG_R3, INS_OPTS_SCALABLE_S,
INS_SCALABLE_OPTS_LSL_N); // ST1W {<Zt>.<T>}, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
theEmitter->emitIns_R_R_R_R(INS_sve_st1w, EA_SCALABLE, REG_V2, REG_P3, REG_R4, REG_R5, INS_OPTS_SCALABLE_D,
INS_SCALABLE_OPTS_LSL_N); // ST1W {<Zt>.<T>}, <Pg>, [<Xn|SP>, <Xm>, LSL #2]

// IF_SVE_JJ_4A
theEmitter->emitIns_R_R_R_R(INS_sve_st1d, EA_SCALABLE, REG_V0, REG_P1, REG_R2, REG_V3, INS_OPTS_SCALABLE_D_UXTW,
INS_SCALABLE_OPTS_MOD_N); // ST1D {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #3]
theEmitter->emitIns_R_R_R_R(INS_sve_st1d, EA_SCALABLE, REG_V0, REG_P1, REG_R2, REG_V3, INS_OPTS_SCALABLE_D_SXTW,
INS_SCALABLE_OPTS_MOD_N); // ST1D {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #3]
theEmitter->emitIns_R_R_R_R(INS_sve_st1h, EA_SCALABLE, REG_V3, REG_P1, REG_R5, REG_V4, INS_OPTS_SCALABLE_S_UXTW,
INS_SCALABLE_OPTS_MOD_N); // ST1H {<Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #1]
theEmitter->emitIns_R_R_R_R(INS_sve_st1h, EA_SCALABLE, REG_V3, REG_P1, REG_R5, REG_V4, INS_OPTS_SCALABLE_S_SXTW,
INS_SCALABLE_OPTS_MOD_N); // ST1H {<Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #1]
theEmitter->emitIns_R_R_R_R(INS_sve_st1w, EA_SCALABLE, REG_V0, REG_P3, REG_R1, REG_V2, INS_OPTS_SCALABLE_S_UXTW,
INS_SCALABLE_OPTS_MOD_N); // ST1W {<Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #2]
theEmitter->emitIns_R_R_R_R(INS_sve_st1w, EA_SCALABLE, REG_V0, REG_P3, REG_R1, REG_V2, INS_OPTS_SCALABLE_S_SXTW,
INS_SCALABLE_OPTS_MOD_N); // ST1W {<Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #2]

// IF_SVE_JJ_4A_B
theEmitter->emitIns_R_R_R_R(INS_sve_st1d, EA_SCALABLE, REG_V3, REG_P1, REG_R2, REG_V5,
INS_OPTS_SCALABLE_D_UXTW); // ST1D {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_st1d, EA_SCALABLE, REG_V3, REG_P1, REG_R2, REG_V5,
INS_OPTS_SCALABLE_D_SXTW); // ST1D {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_st1h, EA_SCALABLE, REG_V2, REG_P3, REG_R1, REG_V4, INS_OPTS_SCALABLE_D_UXTW,
INS_SCALABLE_OPTS_MOD_N); // ST1H {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #1]
theEmitter->emitIns_R_R_R_R(INS_sve_st1h, EA_SCALABLE, REG_V2, REG_P3, REG_R1, REG_V4, INS_OPTS_SCALABLE_D_SXTW,
INS_SCALABLE_OPTS_MOD_N); // ST1H {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #1]
theEmitter->emitIns_R_R_R_R(INS_sve_st1w, EA_SCALABLE, REG_V1, REG_P4, REG_R2, REG_V3, INS_OPTS_SCALABLE_D_UXTW,
INS_SCALABLE_OPTS_MOD_N); // ST1W {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #2]
theEmitter->emitIns_R_R_R_R(INS_sve_st1w, EA_SCALABLE, REG_V1, REG_P4, REG_R2, REG_V3, INS_OPTS_SCALABLE_D_SXTW,
INS_SCALABLE_OPTS_MOD_N); // ST1W {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #2]

// IF_SVE_JJ_4A_C
//theEmitter->emitIns_R_R_R_R(INS_sve_st1h, EA_SCALABLE, REG_V1, REG_P5, REG_R1, REG_V3, INS_OPTS_SCALABLE_D_UXTW); // ST1H {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]
//theEmitter->emitIns_R_R_R_R(INS_sve_st1h, EA_SCALABLE, REG_V1, REG_P5, REG_R1, REG_V3, INS_OPTS_SCALABLE_D_SXTW); // ST1H {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]
//theEmitter->emitIns_R_R_R_R(INS_sve_st1w, EA_SCALABLE, REG_V0, REG_P2, REG_R3, REG_V4, INS_OPTS_SCALABLE_D_UXTW); // ST1W {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]
//theEmitter->emitIns_R_R_R_R(INS_sve_st1w, EA_SCALABLE, REG_V0, REG_P2, REG_R3, REG_V4, INS_OPTS_SCALABLE_D_SXTW); // ST1W {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]

//// IF_SVE_JJ_4A_D
//theEmitter->emitIns_R_R_R_R(INS_sve_st1h, EA_SCALABLE, REG_V7, REG_P5, REG_R4, REG_V1,
// INS_OPTS_SCALABLE_B); // ST1H {<Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod>]
//theEmitter->emitIns_R_R_R_R(INS_sve_st1w, EA_SCALABLE, REG_V1, REG_P2, REG_R3, REG_V2,
// INS_OPTS_SCALABLE_B); // ST1W {<Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod>]

//// IF_SVE_JK_4A
//theEmitter->emitIns_R_R_R_R(INS_sve_st1b, EA_SCALABLE, REG_V4, REG_P2, REG_R0, REG_V1,
// INS_OPTS_SCALABLE_B); // ST1B {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]

//// IF_SVE_JK_4A_B
//theEmitter->emitIns_R_R_R_R(INS_sve_st1b, EA_SCALABLE, REG_V1, REG_P4, REG_R3, REG_V0,
// INS_OPTS_SCALABLE_B); // ST1B {<Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod>]

//// IF_SVE_JN_3A
//theEmitter->emitIns_R_R_R_I(INS_sve_st1b, EA_SCALABLE, REG_V3, REG_P2, REG_R1, 5,
// INS_OPTS_SCALABLE_B); // ST1B {<Zt>.<T>}, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
//theEmitter->emitIns_R_R_R_I(INS_sve_st1h, EA_SCALABLE, REG_V0, REG_P3, REG_R4, 5,
// INS_OPTS_SCALABLE_B); // ST1H {<Zt>.<T>}, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]

//// IF_SVE_JN_3B
//theEmitter->emitIns_R_R_R_I(INS_sve_st1w, EA_SCALABLE, REG_V2, REG_P1, REG_R3, 5,
// INS_OPTS_SCALABLE_B); // ST1W {<Zt>.<T>}, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
}

#endif // defined(TARGET_ARM64) && defined(DEBUG)
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