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Add encoding for ARM64 IF_SVE_CJ_2A instruction group #97885

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merged 7 commits into from
Feb 7, 2024
Merged

Add encoding for ARM64 IF_SVE_CJ_2A instruction group #97885

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e37b1a0
Add encoding for ARM64 IF_SVE_CJ_2A instruction group
snickolls-arm Feb 1, 2024
9ec656b
Merge branch 'dotnet:main' into github-IF_SVE_CJ_2A
snickolls-arm Feb 2, 2024
56ece2c
Merge branch 'main' into github-IF_SVE_CJ_2A
snickolls-arm Feb 5, 2024
c4f425e
Merge remote-tracking branch 'origin/main' into github-IF_SVE_CJ_2A
kunalspathak Feb 5, 2024
7a303d1
fix merge conflicts
kunalspathak Feb 5, 2024
6d31fcb
Merge branch 'main' into github-IF_SVE_CJ_2A
snickolls-arm Feb 7, 2024
ab610b4
Fix conflicts
snickolls-arm Feb 1, 2024
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10 changes: 10 additions & 0 deletions src/coreclr/jit/codegenarm64test.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4725,6 +4725,16 @@ void CodeGen::genArm64EmitterUnitTestsSve()
theEmitter->emitIns_R_R_R(INS_sve_lsr, EA_SCALABLE, REG_V0, REG_P0, REG_V0, INS_OPTS_SCALABLE_S,
INS_SCALABLE_OPTS_WIDE); // LSR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.D

// IF_SVE_CJ_2A
theEmitter->emitIns_R_R(INS_sve_rev, EA_SCALABLE, REG_P1, REG_P2,
INS_OPTS_SCALABLE_B); // REV <Pd>.<T>, <Pn>.<T>
theEmitter->emitIns_R_R(INS_sve_rev, EA_SCALABLE, REG_P4, REG_P5,
INS_OPTS_SCALABLE_H); // REV <Pd>.<T>, <Pn>.<T>
theEmitter->emitIns_R_R(INS_sve_rev, EA_SCALABLE, REG_P3, REG_P7,
INS_OPTS_SCALABLE_S); // REV <Pd>.<T>, <Pn>.<T>
theEmitter->emitIns_R_R(INS_sve_rev, EA_SCALABLE, REG_P0, REG_P6,
INS_OPTS_SCALABLE_D); // REV <Pd>.<T>, <Pn>.<T>

// IF_SVE_CK_2A
theEmitter->emitIns_R_R(INS_sve_punpkhi, EA_SCALABLE, REG_P1, REG_P7); // PUNPKHI <Pd>.H, <Pn>.B
theEmitter->emitIns_R_R(INS_sve_punpklo, EA_SCALABLE, REG_P5, REG_P3); // PUNPKLO <Pd>.H, <Pn>.B
Expand Down
49 changes: 38 additions & 11 deletions src/coreclr/jit/emitarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1102,6 +1102,14 @@ void emitter::emitInsSanityCheck(instrDesc* id)
assert(isPredicateRegister(id->idReg3())); // MMMM
break;

case IF_SVE_CJ_2A: // ........xx...... .......NNNN.DDDD -- SVE reverse predicate elements
elemsize = id->idOpSize();
assert(isScalableVectorSize(elemsize));
assert(insOptsScalableStandard(id->idInsOpt())); // xx
assert(isPredicateRegister(id->idReg1())); // DDDD
assert(isPredicateRegister(id->idReg2())); // NNNN
break;

// Scalable, 4 regs, to predicate register.
case IF_SVE_CX_4A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE integer compare vectors
elemsize = id->idOpSize();
Expand Down Expand Up @@ -7893,6 +7901,13 @@ void emitter::emitIns_R_R(instruction ins,
fmt = IF_SVE_DG_2A;
break;

case INS_sve_rev:
assert(insOptsScalableStandard(opt));
assert(isPredicateRegister(reg1)); // DDDD
assert(isPredicateRegister(reg2)); // NNNN
fmt = IF_SVE_CJ_2A;
break;

case INS_sve_ptest:
assert(opt == INS_OPTS_SCALABLE_B);
assert(isPredicateRegister(reg1)); // gggg
Expand Down Expand Up @@ -16293,6 +16308,7 @@ void emitter::emitIns_Call(EmitCallType callType,
case IF_SVE_CF_2C:
case IF_SVE_CF_2D:
case IF_SVE_CI_3A:
case IF_SVE_CJ_2A:
case IF_SVE_DE_1A:
case IF_SVE_DH_1A:
case IF_SVE_DJ_1A:
Expand Down Expand Up @@ -19884,13 +19900,6 @@ BYTE* emitter::emitOutput_InstrSve(BYTE* dst, instrDesc* id)

switch (fmt)
{
case IF_SVE_CK_2A: // ................ .......NNNN.DDDD -- SVE unpack predicate elements
code = emitInsCodeSve(ins, fmt);
code |= insEncodeReg_P_3_to_0(id->idReg1()); // DDDD
code |= insEncodeReg_P_8_to_5(id->idReg2()); // NNNN
dst += emitOutput_Instr(dst, code);
break;

// Scalable.
case IF_SVE_AA_3A: // ........xx...... ...gggmmmmmddddd -- SVE bitwise logical operations (predicated)
case IF_SVE_AB_3A: // ........xx...... ...gggmmmmmddddd -- SVE integer add/subtract vectors (predicated)
Expand Down Expand Up @@ -20030,6 +20039,21 @@ BYTE* emitter::emitOutput_InstrSve(BYTE* dst, instrDesc* id)
dst += emitOutput_Instr(dst, code);
break;

case IF_SVE_CJ_2A: // ........xx...... .......nnnn.dddd -- SVE reverse predicate elements
code = emitInsCodeSve(ins, fmt);
code |= insEncodeReg_P_3_to_0(id->idReg1()); // DDDD
code |= insEncodeReg_P_8_to_5(id->idReg2()); // NNNN
code |= insEncodeElemsize(optGetSveElemsize(id->idInsOpt())); // xx
dst += emitOutput_Instr(dst, code);
break;

case IF_SVE_CK_2A: // ................ .......NNNN.DDDD -- SVE unpack predicate elements
code = emitInsCodeSve(ins, fmt);
code |= insEncodeReg_P_3_to_0(id->idReg1()); // DDDD
code |= insEncodeReg_P_8_to_5(id->idReg2()); // NNNN
dst += emitOutput_Instr(dst, code);
break;

// Scalable to general register.
case IF_SVE_CO_3A: // ........xx...... ...gggmmmmmddddd -- SVE conditionally extract element to general register
case IF_SVE_CS_3A: // ........xx...... ...gggnnnnnddddd -- SVE extract element to general register
Expand Down Expand Up @@ -23389,6 +23413,12 @@ void emitter::emitDispInsHelp(
break;
}

// <Pd>.<T>, <Pn>.<T>
case IF_SVE_CJ_2A: // ........xx...... .......NNNN.DDDD -- SVE reverse predicate elements
emitDispPredicateReg(id->idReg1(), insGetPredicateType(fmt, 1), id->idInsOpt(), true); // DDDD
emitDispPredicateReg(id->idReg2(), insGetPredicateType(fmt, 2), id->idInsOpt(), false); // NNNN
break;

// <Pdn>.<T>, <Pv>, <Pdn>.<T>
case IF_SVE_DF_2A: // ........xx...... .......VVVV.DDDD -- SVE predicate next active
emitDispPredicateReg(id->idReg1(), insGetPredicateType(fmt, 1), id->idInsOpt(), true); // DDDD
Expand Down Expand Up @@ -26349,10 +26379,7 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
break;

case IF_SVE_CI_3A: // ........xx..MMMM .......NNNN.DDDD -- SVE permute predicate elements
result.insThroughput = PERFSCORE_THROUGHPUT_2C;
result.insLatency = PERFSCORE_LATENCY_2C;
break;

case IF_SVE_CJ_2A: // ........xx...... .......NNNN.DDDD -- SVE reverse predicate elements
case IF_SVE_CK_2A: // ................ .......NNNN.DDDD -- SVE unpack predicate elements
result.insThroughput = PERFSCORE_THROUGHPUT_2C;
result.insLatency = PERFSCORE_LATENCY_2C;
Expand Down
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