[ARM Decoding] SIMD load instruction should be valid

[nathanhjay]

The following is an example of a SIMD load instruction that should be valid but is decoded as invalid by Dyninst.

Bytes: 84 e1 fd 4d
Expected Output: ld2r {v4.16b, v5.16b}, [x12]

[ssunny7]

@nathanhjay could you check the expected output again?

According to what I'm seeing in the manual, this should be decoded as
LD4R {V4.16B, V5.16B, V6.16B, V7.16B}, [X12], X29

[nathanhjay]

Oh, sorry, you're right. That issue appeared for two instructions. The correct decoding of those bytes it:
ld4r {v4.16b, v5.16b, v6.16b, v7.16b}, [x12], x29

[ssunny7]

Fixed by commit 08cff7b.

[nathanhjay]

@ssunny7 I'll close this issue because the instruction now decodes as valid, but there is an extra operand and a few formatting issues in general. Here's that same instruction now:

Bytes: 84 e1 fd 4d
Dyninst: ld4r q4, q5, q6, q7, [x12], x29, x12
Expected: ld4r {v4.16b, v5.16b, v6.16b, v7.16b}, [x12], x29
Also Valid: ld4r {v4.16b-v7.16b}, [x12], x29