phy/ecp5rgmii.py: Add support for dynamic link speeds

liteeth/mac/core.py

@@ -8,6 +8,8 @@
 # Copyright (c) 2023 LumiGuide Fietsdetectie B.V. <[email protected]>
 # SPDX-License-Identifier: BSD-2-Clause
 
+import math
+
 from liteeth.common import *
 from liteeth.mac import gap, preamble, crc, padding, last_be
 from liteeth.phy.model import LiteEthPHYModel
@@ -103,7 +105,14 @@ def add_preamble(self):
                 self.pipeline.append(tx_preamble)
 
             def add_gap(self):
-                tx_gap = gap.LiteEthMACGap(phy_dw)
+                # Some phys, ECP5 for example, have a byte time enable to support
+                # dynamic link speeds.
+                # In the gap inserter we need to ensure this is enable holds for
+                # the gap counter. If not we would insert a gap that might be too
+                # short.
+                default_gap = Constant(math.ceil(eth_interpacket_gap/(phy_dw//8)))
+                gap_len = getattr(phy, "gap", default_gap)
+                tx_gap = gap.LiteEthMACGap(phy_dw, gap_len)
                 tx_gap = ClockDomainsRenamer("eth_tx")(tx_gap)
                 self.submodules += tx_gap
                 self.pipeline.append(tx_gap)

liteeth/mac/gap.py

@@ -4,35 +4,34 @@
 # Copyright (c) 2015-2021 Florent Kermarrec <[email protected]>
 # Copyright (c) 2015-2017 Sebastien Bourdeauducq <[email protected]>
 # Copyright (c) 2018 whitequark <[email protected]>
-# SPDX-License-Identifier: BSD-2-Clause
+# Copyright (c) 2023 LumiGuide Fietsdetectie B.V. <[email protected]>
 
-import math
+# SPDX-License-Identifier: BSD-2-Clause
 
 from liteeth.common import *
 
 # MAC Gap ------------------------------------------------------------------------------------------
 
 class LiteEthMACGap(Module):
-    def __init__(self, dw):
+    def __init__(self, dw, gap=None):
         self.sink   = sink   = stream.Endpoint(eth_phy_description(dw))
         self.source = source = stream.Endpoint(eth_phy_description(dw))
 
         # # #
-
-        gap     = math.ceil(eth_interpacket_gap/(dw//8))
-        counter = Signal(max=gap, reset_less=True)
+        counter_bits, _ = value_bits_sign(gap)
+        counter = Signal(max=2**counter_bits, reset_less=True)
 
         self.submodules.fsm = fsm = FSM(reset_state="COPY")
         fsm.act("COPY",
-            NextValue(counter, 0),
+            NextValue(counter, gap),
             sink.connect(source),
             If(sink.valid & sink.last & sink.ready,
                 NextState("GAP")
             )
         )
         fsm.act("GAP",
-            NextValue(counter, counter + 1),
-            If(counter == (gap-1),
+            NextValue(counter, counter - 1),
+            If(counter == 1,
                 NextState("COPY")
             )
         )