mac/core/LiteEthMACCore: Switch CDC to ClockDomainCrossing and reduce…

… buffering.
enjoy-digital · Jul 16, 2021 · 72dd7bf · 72dd7bf
1 parent 66fcad1
commit 72dd7bf
Showing 1 changed file with 3 additions and 4 deletions.
diff --git a/liteeth/mac/core.py b/liteeth/mac/core.py
@@ -103,10 +103,9 @@ def __init__(self, phy, dw, endianness="big", with_preamble_crc=True, with_paddi
             rx_pipeline += [rx_converter]
 
         # Cross Domain Crossing
-        tx_cdc = stream.AsyncFIFO(eth_phy_description(dw), 64)
-        rx_cdc = stream.AsyncFIFO(eth_phy_description(dw), 64)
-        self.submodules += ClockDomainsRenamer({"write": "sys", "read": "eth_tx"})(tx_cdc)
-        self.submodules += ClockDomainsRenamer({"write": "eth_rx", "read": "sys"})(rx_cdc)
+        tx_cdc = stream.ClockDomainCrossing(eth_phy_description(dw), cd_from="sys",    cd_to="eth_tx", depth=32)
+        rx_cdc = stream.ClockDomainCrossing(eth_phy_description(dw), cd_from="eth_rx", cd_to="sys",    depth=32)
+        self.submodules += tx_cdc, rx_cdc
         tx_pipeline += [tx_cdc]
         rx_pipeline += [rx_cdc]