Add/edit PSRAM-related SPI registers (#262)

* WIP state (PSRAM-related SPI regs)

* WIP state (SPI registers access)

* Make arrays from CSx_DIS on every chip

esp32/src/spi0.rs

@@ -540,7 +540,7 @@ pub mod dma_rstatus;
 pub type DMA_TSTATUS = crate::Reg<dma_tstatus::DMA_TSTATUS_SPEC>;
 #[doc = ""]
 pub mod dma_tstatus;
-#[doc = "DATE (r) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"]
+#[doc = "DATE (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"]
 pub type DATE = crate::Reg<date::DATE_SPEC>;
 #[doc = ""]
 pub mod date;

esp32/src/spi0/date.rs

@@ -1,5 +1,7 @@
 #[doc = "Register `DATE` reader"]
 pub type R = crate::R<DATE_SPEC>;
+#[doc = "Register `DATE` writer"]
+pub type W = crate::W<DATE_SPEC>;
 #[doc = "Field `DATE` reader - SPI register version."]
 pub type DATE_R = crate::FieldReader<u32>;
 impl R {
@@ -15,13 +17,20 @@ impl core::fmt::Debug for R {
         f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
-#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+impl W {}
+#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DATE_SPEC;
 impl crate::RegisterSpec for DATE_SPEC {
     type Ux = u32;
 }
 #[doc = "`read()` method returns [`date::R`](R) reader structure"]
 impl crate::Readable for DATE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"]
+impl crate::Writable for DATE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
 #[doc = "`reset()` method sets DATE to value 0x0160_4270"]
 impl crate::Resettable for DATE_SPEC {
     const RESET_VALUE: u32 = 0x0160_4270;

esp32/src/spi0/pin.rs

@@ -2,18 +2,10 @@
 pub type R = crate::R<PIN_SPEC>;
 #[doc = "Register `PIN` writer"]
 pub type W = crate::W<PIN_SPEC>;
-#[doc = "Field `CS0_DIS` reader - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin"]
-pub type CS0_DIS_R = crate::BitReader;
-#[doc = "Field `CS0_DIS` writer - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin"]
-pub type CS0_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CS1_DIS` reader - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin"]
-pub type CS1_DIS_R = crate::BitReader;
-#[doc = "Field `CS1_DIS` writer - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin"]
-pub type CS1_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CS2_DIS` reader - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin"]
-pub type CS2_DIS_R = crate::BitReader;
-#[doc = "Field `CS2_DIS` writer - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin"]
-pub type CS2_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CS_DIS(0-2)` reader - Set this bit to raise high SPI_CS%s pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS%s is in low level when SPI1 transfer starts"]
+pub type CS_DIS_R = crate::BitReader;
+#[doc = "Field `CS_DIS(0-2)` writer - Set this bit to raise high SPI_CS%s pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS%s is in low level when SPI1 transfer starts"]
+pub type CS_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `CK_DIS` reader - 1: spi clk out disable 0: spi clk out enable"]
 pub type CK_DIS_R = crate::BitReader;
 #[doc = "Field `CK_DIS` writer - 1: spi clk out disable 0: spi clk out enable"]
@@ -35,20 +27,35 @@ pub type CS_KEEP_ACTIVE_R = crate::BitReader;
 #[doc = "Field `CS_KEEP_ACTIVE` writer - spi cs line keep low when the bit is set."]
 pub type CS_KEEP_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
-    #[doc = "Bit 0 - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin"]
+    #[doc = "Set this bit to raise high SPI_CS(0-2) pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS(0-2) is in low level when SPI1 transfer starts"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CS0_DIS` field.</div>"]
     #[inline(always)]
-    pub fn cs0_dis(&self) -> CS0_DIS_R {
-        CS0_DIS_R::new((self.bits & 1) != 0)
+    pub fn cs_dis(&self, n: u8) -> CS_DIS_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CS_DIS_R::new(((self.bits >> n) & 1) != 0)
     }
-    #[doc = "Bit 1 - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin"]
+    #[doc = "Iterator for array of:"]
+    #[doc = "Set this bit to raise high SPI_CS(0-2) pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS(0-2) is in low level when SPI1 transfer starts"]
     #[inline(always)]
-    pub fn cs1_dis(&self) -> CS1_DIS_R {
-        CS1_DIS_R::new(((self.bits >> 1) & 1) != 0)
+    pub fn cs_dis_iter(&self) -> impl Iterator<Item = CS_DIS_R> + '_ {
+        (0..3).map(move |n| CS_DIS_R::new(((self.bits >> n) & 1) != 0))
     }
-    #[doc = "Bit 2 - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin"]
+    #[doc = "Bit 0 - Set this bit to raise high SPI_CS0 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS0 is in low level when SPI1 transfer starts"]
     #[inline(always)]
-    pub fn cs2_dis(&self) -> CS2_DIS_R {
-        CS2_DIS_R::new(((self.bits >> 2) & 1) != 0)
+    pub fn cs0_dis(&self) -> CS_DIS_R {
+        CS_DIS_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS1 is in low level when SPI1 transfer starts"]
+    #[inline(always)]
+    pub fn cs1_dis(&self) -> CS_DIS_R {
+        CS_DIS_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Set this bit to raise high SPI_CS2 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS2 is in low level when SPI1 transfer starts"]
+    #[inline(always)]
+    pub fn cs2_dis(&self) -> CS_DIS_R {
+        CS_DIS_R::new(((self.bits >> 2) & 1) != 0)
     }
     #[doc = "Bit 5 - 1: spi clk out disable 0: spi clk out enable"]
     #[inline(always)]
@@ -80,35 +87,45 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN")
-            .field("cs0_dis", &self.cs0_dis())
-            .field("cs1_dis", &self.cs1_dis())
-            .field("cs2_dis", &self.cs2_dis())
             .field("ck_dis", &self.ck_dis())
             .field("master_cs_pol", &self.master_cs_pol())
             .field("master_ck_sel", &self.master_ck_sel())
             .field("ck_idle_edge", &self.ck_idle_edge())
             .field("cs_keep_active", &self.cs_keep_active())
+            .field("cs0_dis", &self.cs0_dis())
+            .field("cs1_dis", &self.cs1_dis())
+            .field("cs2_dis", &self.cs2_dis())
             .finish()
     }
 }
 impl W {
-    #[doc = "Bit 0 - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin"]
+    #[doc = "Set this bit to raise high SPI_CS(0-2) pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS(0-2) is in low level when SPI1 transfer starts"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CS0_DIS` field.</div>"]
+    #[inline(always)]
+    #[must_use]
+    pub fn cs_dis(&mut self, n: u8) -> CS_DIS_W<PIN_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        CS_DIS_W::new(self, n)
+    }
+    #[doc = "Bit 0 - Set this bit to raise high SPI_CS0 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS0 is in low level when SPI1 transfer starts"]
     #[inline(always)]
     #[must_use]
-    pub fn cs0_dis(&mut self) -> CS0_DIS_W<PIN_SPEC> {
-        CS0_DIS_W::new(self, 0)
+    pub fn cs0_dis(&mut self) -> CS_DIS_W<PIN_SPEC> {
+        CS_DIS_W::new(self, 0)
     }
-    #[doc = "Bit 1 - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin"]
+    #[doc = "Bit 1 - Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS1 is in low level when SPI1 transfer starts"]
     #[inline(always)]
     #[must_use]
-    pub fn cs1_dis(&mut self) -> CS1_DIS_W<PIN_SPEC> {
-        CS1_DIS_W::new(self, 1)
+    pub fn cs1_dis(&mut self) -> CS_DIS_W<PIN_SPEC> {
+        CS_DIS_W::new(self, 1)
     }
-    #[doc = "Bit 2 - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin"]
+    #[doc = "Bit 2 - Set this bit to raise high SPI_CS2 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS2 is in low level when SPI1 transfer starts"]
     #[inline(always)]
     #[must_use]
-    pub fn cs2_dis(&mut self) -> CS2_DIS_W<PIN_SPEC> {
-        CS2_DIS_W::new(self, 2)
+    pub fn cs2_dis(&mut self) -> CS_DIS_W<PIN_SPEC> {
+        CS_DIS_W::new(self, 2)
     }
     #[doc = "Bit 5 - 1: spi clk out disable 0: spi clk out enable"]
     #[inline(always)]

esp32/src/spi0/user1.rs

@@ -8,6 +8,8 @@ pub type USR_DUMMY_CYCLELEN_R = crate::FieldReader;
 pub type USR_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
 #[doc = "Field `USR_ADDR_BITLEN` reader - The length in bits of address phase. The register value shall be (bit_num-1)."]
 pub type USR_ADDR_BITLEN_R = crate::FieldReader;
+#[doc = "Field `USR_ADDR_BITLEN` writer - The length in bits of address phase. The register value shall be (bit_num-1)."]
+pub type USR_ADDR_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
 impl R {
     #[doc = "Bits 0:7 - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1)."]
     #[inline(always)]
@@ -36,6 +38,12 @@ impl W {
     pub fn usr_dummy_cyclelen(&mut self) -> USR_DUMMY_CYCLELEN_W<USER1_SPEC> {
         USR_DUMMY_CYCLELEN_W::new(self, 0)
     }
+    #[doc = "Bits 26:31 - The length in bits of address phase. The register value shall be (bit_num-1)."]
+    #[inline(always)]
+    #[must_use]
+    pub fn usr_addr_bitlen(&mut self) -> USR_ADDR_BITLEN_W<USER1_SPEC> {
+        USR_ADDR_BITLEN_W::new(self, 26)
+    }
 }
 #[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`user1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`user1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct USER1_SPEC;

esp32/svd/patches/esp32.yaml

@@ -108,6 +108,24 @@ SENS:
   _include: ../../../common_patches/sens.yaml
 
 SPI0:
+  _modify:
+    DATE:
+      access: read-write
+  USER1:
+    _modify:
+      USR_ADDR_BITLEN:
+        access: read-write
+  PIN:
+    _delete: ["CS0_DIS", "CS1_DIS", "CS2_DIS"]
+    _add:
+      CS%s_DIS:
+        dim: 3
+        dimIndex: 0-2
+        dimIncrement: 0x1
+        description: "Set this bit to raise high SPI_CS%s pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS%s is in low level when SPI1 transfer starts"
+        bitOffset: 0
+        bitWidth: 1
+        access: read-write
   _include:
     - ../../../common_patches/spi_dma_int_strip.yaml
     - ../../../common_patches/spi_w.yaml

esp32s2/src/spi0.rs

@@ -18,11 +18,11 @@ pub struct RegisterBlock {
     slave1: SLAVE1,
     slv_wrbuf_dlen: SLV_WRBUF_DLEN,
     slv_rdbuf_dlen: SLV_RDBUF_DLEN,
-    slv_rd_byte: SLV_RD_BYTE,
+    _reserved_16_cache_sctrl: [u8; 0x04],
     fsm: FSM,
-    hold: HOLD,
-    dma_conf: DMA_CONF,
-    dma_out_link: DMA_OUT_LINK,
+    _reserved_18_hold: [u8; 0x04],
+    _reserved_19_dma_conf: [u8; 0x04],
+    _reserved_20_sram_clk: [u8; 0x04],
     dma_in_link: DMA_IN_LINK,
     dma_int_ena: DMA_INT_ENA,
     dma_int_raw: DMA_INT_RAW,
@@ -134,30 +134,50 @@ impl RegisterBlock {
     pub const fn slv_rdbuf_dlen(&self) -> &SLV_RDBUF_DLEN {
         &self.slv_rdbuf_dlen
     }
+    #[doc = "0x40 - SPI Memory Cache SCTRL Register"]
+    #[inline(always)]
+    pub const fn cache_sctrl(&self) -> &CACHE_SCTRL {
+        unsafe { &*(self as *const Self).cast::<u8>().add(64).cast() }
+    }
     #[doc = "0x40 - SPI interrupt control register"]
     #[inline(always)]
     pub const fn slv_rd_byte(&self) -> &SLV_RD_BYTE {
-        &self.slv_rd_byte
+        unsafe { &*(self as *const Self).cast::<u8>().add(64).cast() }
     }
     #[doc = "0x44 - SPI master status and DMA read byte control register"]
     #[inline(always)]
     pub const fn fsm(&self) -> &FSM {
         &self.fsm
     }
+    #[doc = "0x48 - SPI Memory SRAM DRD CMD Register"]
+    #[inline(always)]
+    pub const fn sram_drd_cmd(&self) -> &SRAM_DRD_CMD {
+        unsafe { &*(self as *const Self).cast::<u8>().add(72).cast() }
+    }
     #[doc = "0x48 - SPI hold register"]
     #[inline(always)]
     pub const fn hold(&self) -> &HOLD {
-        &self.hold
+        unsafe { &*(self as *const Self).cast::<u8>().add(72).cast() }
+    }
+    #[doc = "0x4c - SPI Memory SRAM DWR CMD Register"]
+    #[inline(always)]
+    pub const fn sram_dwr_cmd(&self) -> &SRAM_DWR_CMD {
+        unsafe { &*(self as *const Self).cast::<u8>().add(76).cast() }
     }
     #[doc = "0x4c - SPI DMA control register"]
     #[inline(always)]
     pub const fn dma_conf(&self) -> &DMA_CONF {
-        &self.dma_conf
+        unsafe { &*(self as *const Self).cast::<u8>().add(76).cast() }
+    }
+    #[doc = "0x50 - SPI Memory SRAM Clock Register"]
+    #[inline(always)]
+    pub const fn sram_clk(&self) -> &SRAM_CLK {
+        unsafe { &*(self as *const Self).cast::<u8>().add(80).cast() }
     }
     #[doc = "0x50 - SPI DMA TX link configuration"]
     #[inline(always)]
     pub const fn dma_out_link(&self) -> &DMA_OUT_LINK {
-        &self.dma_out_link
+        unsafe { &*(self as *const Self).cast::<u8>().add(80).cast() }
     }
     #[doc = "0x54 - SPI DMA RX link configuration"]
     #[inline(always)]
@@ -502,3 +522,19 @@ pub mod lcd_d_num;
 pub type REG_DATE = crate::Reg<reg_date::REG_DATE_SPEC>;
 #[doc = "SPI version control"]
 pub mod reg_date;
+#[doc = "CACHE_SCTRL (rw) register accessor: SPI Memory Cache SCTRL Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_sctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_sctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_sctrl`] module"]
+pub type CACHE_SCTRL = crate::Reg<cache_sctrl::CACHE_SCTRL_SPEC>;
+#[doc = "SPI Memory Cache SCTRL Register"]
+pub mod cache_sctrl;
+#[doc = "SRAM_DWR_CMD (rw) register accessor: SPI Memory SRAM DWR CMD Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_dwr_cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_dwr_cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_dwr_cmd`] module"]
+pub type SRAM_DWR_CMD = crate::Reg<sram_dwr_cmd::SRAM_DWR_CMD_SPEC>;
+#[doc = "SPI Memory SRAM DWR CMD Register"]
+pub mod sram_dwr_cmd;
+#[doc = "SRAM_DRD_CMD (rw) register accessor: SPI Memory SRAM DRD CMD Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_drd_cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_drd_cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_drd_cmd`] module"]
+pub type SRAM_DRD_CMD = crate::Reg<sram_drd_cmd::SRAM_DRD_CMD_SPEC>;
+#[doc = "SPI Memory SRAM DRD CMD Register"]
+pub mod sram_drd_cmd;
+#[doc = "SRAM_CLK (rw) register accessor: SPI Memory SRAM Clock Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_clk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_clk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_clk`] module"]
+pub type SRAM_CLK = crate::Reg<sram_clk::SRAM_CLK_SPEC>;
+#[doc = "SPI Memory SRAM Clock Register"]
+pub mod sram_clk;