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Fix inline assembly test #241

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Fix inline assembly test #241

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fe7321d
Add XTENSA_ALLOWED_FEATURES to supported_target_features
taiki-e Oct 27, 2024
e2b0662
Fix inline assembly test
taiki-e Oct 27, 2024
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1 change: 1 addition & 0 deletions compiler/rustc_target/src/target_features.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -566,6 +566,7 @@ impl super::spec::Target {
"csky" => CSKY_ALLOWED_FEATURES,
"loongarch64" => LOONGARCH_ALLOWED_FEATURES,
"s390x" => IBMZ_ALLOWED_FEATURES,
"xtensa" => XTENSA_ALLOWED_FEATURES,
_ => &[],
}
}
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27 changes: 13 additions & 14 deletions tests/assembly/asm/xtensa-types.rs
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@@ -1,9 +1,8 @@
// min-llvm-version: 10.0.1
// assembly-output: emit-asm
// compile-flags: --target xtensa-esp32-none-elf
// needs-llvm-components: xtensa
//@ assembly-output: emit-asm
//@ compile-flags: --target xtensa-esp32-none-elf
//@ needs-llvm-components: xtensa

#![feature(no_core, lang_items, rustc_attrs, repr_simd)]
#![feature(no_core, lang_items, rustc_attrs, repr_simd, asm_experimental_arch)]
#![crate_type = "rlib"]
#![no_core]
#![allow(asm_sub_register, non_camel_case_types)]
Expand Down Expand Up @@ -68,25 +67,25 @@ macro_rules! check_general_reg {

// CHECK-LABEL: reg_i8:
// CHECK: #APP
// CHECK: mov a{{[0-9]+}}, a{{[0-9]+}}
// CHECK: or a{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}}
// CHECK: #NO_APP
check_general_reg!(reg_i8 i8 reg "mov");

// CHECK-LABEL: reg_i16:
// CHECK: #APP
// CHECK: mov a{{[0-9]+}}, a{{[0-9]+}}
// CHECK: or a{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}}
// CHECK: #NO_APP
check_general_reg!(reg_i16 i16 reg "mov");

// CHECK-LABEL: reg_i32:
// CHECK: #APP
// CHECK: mov a{{[0-9]+}}, a{{[0-9]+}}
// CHECK: or a{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}}
// CHECK: #NO_APP
check_general_reg!(reg_i32 i32 reg "mov");

// CHECK-LABEL: reg_ptr:
// CHECK: #APP
// CHECK: mov a{{[0-9]+}}, a{{[0-9]+}}
// CHECK: or a{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}}
// CHECK: #NO_APP
check_general_reg!(reg_ptr ptr reg "mov");

Expand All @@ -111,25 +110,25 @@ macro_rules! check_explicit_reg {

// CHECK-LABEL: a5_i8:
// CHECK: #APP
// CHECK: mov a5, a5
// CHECK: or a5, a5, a5
// CHECK: #NO_APP
check_explicit_reg!(a5_i8 i8 "a5" "mov");

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Btw, this test actually appears to be doing what the ISA says it should not do.
Xtensa Instruction Set Architecture (ISA) Reference Manual (436 page) says:

ar and as should not specify the same register due to the MOV.N restriction.

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Interestingly the official ISA from cadence omits this line: https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/tools/silicon-solutions/compute-ip/isa-summary.pdf (page 495). I'll ask the LLVM team what their reference is.

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Ah, it seems that what I was looking at was an old manual.

https://web.archive.org/web/20241005102231/https://0x04.net/~mwk/doc/xtensa.pdf (page 2)

Issue Date: 4/2010
RC-2010.1 Release
PD-09-0801-10-01

https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/tools/silicon-solutions/compute-ip/isa-summary.pdf (page 2)

Product Release:RI-2021.8
Last Updated:04/2022
Modification: 737871

// CHECK-LABEL: a5_i16:
// CHECK: #APP
// CHECK: mov a5, a5
// CHECK: or a5, a5, a5
// CHECK: #NO_APP
check_explicit_reg!(a5_i16 i16 "a5" "mov");

// CHECK-LABEL: a0_i32:
// CHECK-LABEL: a5_i32:
// CHECK: #APP
// CHECK: mov a5, a5
// CHECK: or a5, a5, a5
// CHECK: #NO_APP
check_explicit_reg!(a5_i32 i32 "a5" "mov");

// CHECK-LABEL: a5_ptr:
// CHECK: #APP
// CHECK: mov a5, a5
// CHECK: or a5, a5, a5
// CHECK: #NO_APP
check_explicit_reg!(a5_ptr ptr "a5" "mov");

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