Xtensa patches (15.x) (Do not merge, PR created for easier review only) #62

gerekon · 2022-09-25T21:24:39Z

No description provided.

Add Xtensa.td, XtensaInstrInfo.td etc. Currently add just part of Core Instructions like ALU, processor control, memory barrier and some move instructions. Add instructions formats and basic registers.

Add FDE CFI encoding for Xtensa.

Add instruction printer and basic tests of the Xtensa instructions.

Add td descriptions of the Xtensa shift/load/store instructions.

Add relocations and fixups support in object files generation. Modify tests to support new instructions. Add tests for relocations and fixups.

Initial codegen support for simple ALU operations.

Lower ConstantPool, GlobalAddress, BlockAddress and JumpTable. Implement lowering of External and JumpTable symbols to MCInst representation.

Implement lowering of dynamic_stackalloc, stacksave, stackrestore.

Also lower SHL, SRA, SRL with register operands.

Implement load unsigned 8-bit pseudo operation. Implement extending loads patterns extloadi1/i8/i16.

Add support for llvm.{frameaddress,returnaddress} intrinsics.

Implement volatile load/store from/to volatile memory location.

… release pipelines

- Forces 128bit arguments to have 128bit alignment as per the Xtensa ABI in LLVM & Clang. - Adds a check in the Xtensa calling convention to ensure 128bit aligned arguments are always passed as the first argument _or_ passed via the stack.

Fix register liveness in emitAtomicRMW function.

If block with LOOPEND instruction has smaller offset then loop heeader block then try to find appropriate place for LOOPEND instruction after loop header

Closes #11

…ested in https://reviews.llvm.org/D64833.

For large mcmodel always emit contsant pool just before code.

Create block and insert it before loop end address as target for jump/branch instruction to avoid premature exit from loop.

The constant islands pass is always executed for large code model. Also currently is disabled support of the hardware loops for large code model, need to add support for hwloops in constant islands pass in future.

Disable hwloop by default and fix hwloop tests.

Add different diagnotstics messages for different branch relocations fixups.

gerekon · 2023-04-26T18:51:20Z

Close in favor of #67

andreisfr added 30 commits September 12, 2022 23:36

[Xtensa] Recognize Xtensa in triple parsing code.

87df1ee

[Xtensa] Add definitions and relocs for Xtensa ELF.

0def3c2

[Xtensa] Add initial version of the Xtensa backend.

41bfeb8

[Xtensa] Add basic *td files with Xtensa architecture description.

7029d28

Add Xtensa.td, XtensaInstrInfo.td etc. Currently add just part of Core Instructions like ALU, processor control, memory barrier and some move instructions. Add instructions formats and basic registers.

[Xtensa] Add Xtensa MCTargetDescr initial functionality.

97bba5f

Add FDE CFI encoding for Xtensa.

[Xtensa] Add Xtensa basic assembler parser.

7c4adeb

[Xtensa] Add basic Xtensa instruction printer.

780c83f

Add instruction printer and basic tests of the Xtensa instructions.

[Xtensa] Add shift/load/store instructions.

9fe2aa5

Add td descriptions of the Xtensa shift/load/store instructions.

[Xtensa] Add basic support of Xtensa disassembler.

1fabd10

[Xtensa] Add support of the rest part of Xtensa Core Instructions.

edd85c2

Add relocations and fixups support in object files generation. Modify tests to support new instructions. Add tests for relocations and fixups.

[Xtensa] Initial support of the ALU operations.

a4a95a0

Initial codegen support for simple ALU operations.

[Xtensa] Codegen support for memory operations

5af39bc

[Xtensa] Add Constant Pool

795cad0

[Xtensa] Implement assembler representation of the Constant Pool.

8a353ec

[Xtensa] Implement lowering constants.

9fa51df

[Xtensa] Add support of the Xtensa function calls

074de8e

[Xtensa] Implement lowering ConstantPool and address operations.

57e4efc

Lower ConstantPool, GlobalAddress, BlockAddress and JumpTable. Implement lowering of External and JumpTable symbols to MCInst representation.

[Xtensa] Implement emitPrologue/emitEpilogue

5d2d842

[Xtensa] Lower stack operations

874d395

Implement lowering of dynamic_stackalloc, stacksave, stackrestore.

[Xtensa] Implement lowering SELECT_CC, SETCC

19d5a89

[Xtensa] Support for a variety of additional LLVM IR constructs.

623ab15

[Xtensa] Lower SHIFT PARTS and shift operations.

ffa7c6f

Also lower SHL, SRA, SRL with register operands.

[Xtensa] Implement load pseudo operations and patterns.

a729ef2

Implement load unsigned 8-bit pseudo operation. Implement extending loads patterns extloadi1/i8/i16.

[Xtensa] Support for variable arguments

f6ad2a7

[Xtensa] Implement lowering BR_JT operation

2d31297

[Xtensa] Support for address intrinsics.

18b9007

Add support for llvm.{frameaddress,returnaddress} intrinsics.

[Xtensa] Add basic support for inline asm constraints

dbe85b0

[Xtensa] Implement volatile load/store.

2d3fb99

Implement volatile load/store from/to volatile memory location.

[Xtensa] Implement branch analysis

7152676

[Xtensa] Implement support for the BranchRelaxation

e40c9a1

gerekon and others added 23 commits September 13, 2022 13:22

esp/ci: Move newlib build to separate job

63b6e44

esp/ci: Adds Linux ARM/ARM64 universal toolchain builds

e95d783

riscv/esp: Fixes riscv32-esp toolchain tests

d1b0c88

esp/ci: Upgrade Clang ver to 15

d9ff0ed

esp/ci: Adds support to switch between legacy and universal toolchain…

ab29eaa

… release pipelines

esp/ci: Adds MacOS binaries signing stage

9840a97

[Xtensa] Xtensa ABI 128bit arg alignment

34236f6

- Forces 128bit arguments to have 128bit alignment as per the Xtensa ABI in LLVM & Clang. - Adds a check in the Xtensa calling convention to ensure 128bit aligned arguments are always passed as the first argument _or_ passed via the stack.

[Xtensa] Fix Call ABI for 16 byte alignment.

a9754a1

[Xtensa] Add IR test for 16byte alignment.

0af6dae

esp/ci: Run LLD tests. Output test logs in lld-tests.log

28b26ff

[Xtensa] Fix atomic rmw operation.

4a51f8f

Fix register liveness in emitAtomicRMW function.

[Xtensa] Fix Hardware Loop pass.

32e6411

If block with LOOPEND instruction has smaller offset then loop heeader block then try to find appropriate place for LOOPEND instruction after loop header

[Xtensa] Add LLD linker support

ce430fd

Closes #11

[Xtensa][LLD] add more tests

0e22873

[Xtensa][LLD] Fix J formula

1fa3906

[Xtensa] Adding new invalid tests and changing test structure as requ…

e520bb1

…ested in https://reviews.llvm.org/D64833.

[Xtensa] Add emit constant pool option.

d8fe3d0

[Xtensa] Add support of the mcmodel option.

9b553d7

For large mcmodel always emit contsant pool just before code.

[Xtensa] Fix lowering funnel shift left.

7c941f4

[Xtensa] Make it possible to use -fuse-ld when GCC toolchain is detected

17496a8

esp/ci: Fixes Windows release archives

d4f9df6

esp/ci: Check for OOM failures after build

2378612

[LLD][Xtensa] Cover DIFF{8, 16, 32} relocations.

a07cafd

igrr mentioned this pull request Feb 12, 2023

Merge into main branch rust-lang/rust? esp-rs/rust#89

Open

andreisfr added 4 commits March 30, 2023 01:00

[Xtensa] Fixup hwloop pass

f389074

Create block and insert it before loop end address as target for jump/branch instruction to avoid premature exit from loop.

[Xtensa] Implement constant islands pass

a3ce635

The constant islands pass is always executed for large code model. Also currently is disabled support of the hardware loops for large code model, need to add support for hwloops in constant islands pass in future.

[Xtensa] Disable hardware loops by default.

2989ff7

Disable hwloop by default and fix hwloop tests.

[Xtensa] Improve fixup error messages in asm backend.

1e28f73

Add different diagnotstics messages for different branch relocations fixups.

gerekon closed this Apr 26, 2023

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Xtensa patches (15.x) (Do not merge, PR created for easier review only) #62

Xtensa patches (15.x) (Do not merge, PR created for easier review only) #62

gerekon commented Sep 25, 2022

gerekon commented Apr 26, 2023

Xtensa patches (15.x) (Do not merge, PR created for easier review only) #62

Xtensa patches (15.x) (Do not merge, PR created for easier review only) #62

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gerekon commented Sep 25, 2022

gerekon commented Apr 26, 2023