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@georgantas
georgantas committed Sep 21, 2019
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64 changes: 64 additions & 0 deletions alu.vhd
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;

entity alu is
port( x, y : in std_logic_vector(31 downto 0);
--two input operands
add_sub: in std_logic;
logic_func : in std_logic_vector(1 downto 0);
-- 00 = AND, 01 = OR, 10 = XOR, 11 = NOR
func: in std_logic_vector(1 downto 0);
-- 00 = lui, 01 = setless, 10 = arith, 11 = logic
output: out std_logic_vector(31 downto 0);
overflow: out std_logic;
zero: out std_logic);
end alu;

architecture arch_alu of alu is
signal xy_sub : std_logic_vector(31 downto 0);
signal add_subtract_res : std_logic_vector(32 downto 0);
signal add_subtract_res2 : std_logic_vector(31 downto 0);
signal logic_res : std_logic_vector(31 downto 0);
signal slt_res: std_logic_vector(31 downto 0);
signal lui_res : std_logic_vector(31 downto 0);
signal c_out : std_logic;
signal c_in : std_logic;
begin

xy_sub <= x - y;

c_out <= add_subtract_res(32);
c_in <= add_subtract_res2(31);

with add_sub select
add_subtract_res2 <= ('0' & x(30 downto 0)) + ('0' & y(30 downto 0)) when '0',
('0' & x(30 downto 0)) + ('0' & (-y(30 downto 0))) when others;

with add_sub select
add_subtract_res <= ('0' & x) + ('0' & y) when '0',
('0' & x) + ('0' & (-y)) when others;
with logic_func select
logic_res <= x and y when "00",
x or y when "01",
x xor y when "10",
x nor y when others;


slt_res <= "0000000000000000000000000000000" & xy_sub(31);

lui_res <= y;

with func select
output <= lui_res when "00",
slt_res when "01",
add_subtract_res(31 downto 0) when "10",
logic_res when others;

zero <= '1' when add_subtract_res(31 downto 0) = 0 else '0';
-- and func = "10" else '0';

overflow <= c_out xor c_in;
--when func = "10" else '0';

end arch_alu;
257 changes: 257 additions & 0 deletions control.vhd
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library IEEE;
use IEEE.std_logic_1164.all;

entity control is
port(
opcode : in std_logic_vector(5 downto 0);
op_function : in std_logic_vector(5 downto 0);
reg_write : out std_logic;
reg_dst : out std_logic;
reg_in_src : out std_logic;
alu_src : out std_logic;
add_sub : out std_logic;
data_write : out std_logic;
logic_func : out std_logic_vector(1 downto 0);
func : out std_logic_vector(1 downto 0);
branch_type : out std_logic_vector(1 downto 0);
pc_sel : out std_logic_vector(1 downto 0)
);
end control;

architecture control_arch of control is

begin

process(opcode, op_function)

begin
case opcode is
when "000000" =>
case op_function is
when "100000" =>
reg_write <= '1';
reg_dst <= '1';
reg_in_src <= '1';
alu_src <= '0';
add_sub <= '0';
data_write <= '0';
logic_func <= "00";
func <= "10";
branch_type <= "00";
pc_sel <= "00";
when "100010" =>
reg_write <= '1';
reg_dst <= '1';
reg_in_src <= '1';
alu_src <= '0';
add_sub <= '1';
data_write <= '0';
logic_func <= "00";
func <= "10";
branch_type <= "00";
pc_sel <= "00";
when "101010" =>
reg_write <= '1';
reg_dst <= '1';
reg_in_src <= '1';
alu_src <= '0';
add_sub <= '0';
data_write <= '0';
logic_func <= "00";
func <= "01";
branch_type <= "00";
pc_sel <= "00";
when "100100" =>
reg_write <= '1';
reg_dst <= '1';
reg_in_src <= '1';
alu_src <= '0';
add_sub <= '1';
data_write <= '0';
logic_func <= "00";
func <= "11";
branch_type <= "00";
pc_sel <= "00";
when "100101" =>
reg_write <= '1';
reg_dst <= '1';
reg_in_src <= '1';
alu_src <= '0';
add_sub <= '1';
data_write <= '0';
logic_func <= "00";
func <= "11";
branch_type <= "00";
pc_sel <= "00";
when "100110" =>
reg_write <= '1';
reg_dst <= '1';
reg_in_src <= '1';
alu_src <= '0';
add_sub <= '0';
data_write <= '0';
logic_func <= "01";
func <= "11";
branch_type <= "00";
pc_sel <= "00";
when "100111" =>
reg_write <= '1';
reg_dst <= '1';
reg_in_src <= '1';
alu_src <= '0';
add_sub <= '0';
data_write <= '0';
logic_func <= "11";
func <= "11";
branch_type <= "00";
pc_sel <= "00";
when others =>
reg_write <= '0';
reg_dst <= '1';
reg_in_src <= '0';
alu_src <= '0';
add_sub <= '0';
data_write <= '0';
logic_func <= "00";
func <= "10";
branch_type <= "00";
pc_sel <= "10";
end case;
when "001111" =>
reg_write <= '1';
reg_dst <= '0';
reg_in_src <= '1';
alu_src <= '1';
add_sub <= '0';
data_write <= '0';
logic_func <= "00";
func <= "00";
branch_type <= "00";
pc_sel <= "00";
when "001000" =>
reg_write <= '1';
reg_dst <= '0';
reg_in_src <= '1';
alu_src <= '1';
add_sub <= '0';
data_write <= '0';
logic_func <= "00";
func <= "10";
branch_type <= "00";
pc_sel <= "00";
when "001010" =>
reg_write <= '1';
reg_dst <= '0';
reg_in_src <= '1';
alu_src <= '1';
add_sub <= '0';
data_write <= '0';
logic_func <= "00";
func <= "01";
branch_type <= "00";
pc_sel <= "00";
when "001100" =>
reg_write <= '1';
reg_dst <= '0';
reg_in_src <= '1';
alu_src <= '1';
add_sub <= '0';
data_write <= '0';
logic_func <= "00";
func <= "11";
branch_type <= "00";
pc_sel <= "00";
when "001101" =>
reg_write <= '1';
reg_dst <= '0';
reg_in_src <= '1';
alu_src <= '1';
add_sub <= '0';
data_write <= '0';
logic_func <= "01";
func <= "11";
branch_type <= "00";
pc_sel <= "00";
when "001110" =>
reg_write <= '1';
reg_dst <= '0';
reg_in_src <= '1';
alu_src <= '1';
add_sub <= '0';
data_write <= '0';
logic_func <= "10";
func <= "11";
branch_type <= "00";
pc_sel <= "00";
when "100011" =>
reg_write <= '1';
reg_dst <= '0';
reg_in_src <= '0';
alu_src <= '1';
add_sub <= '0';
data_write <= '0';
logic_func <= "10";
func <= "10";
branch_type <= "00";
pc_sel <= "00";
when "101011" =>
reg_write <= '0';
reg_dst <= '0';
reg_in_src <= '0';
alu_src <= '1';
add_sub <= '0';
data_write <= '1';
logic_func <= "00";
func <= "10";
branch_type <= "00";
pc_sel <= "00";
when "000010" =>
reg_write <= '0';
reg_dst <= '0';
reg_in_src <= '0';
alu_src <= '1';
add_sub <= '0';
data_write <= '0';
logic_func <= "00";
func <= "10";
branch_type <= "00";
pc_sel <= "01";
when "000001" =>
reg_write <= '0';
reg_dst <= '0';
reg_in_src <= '0';
alu_src <= '0';
add_sub <= '0';
data_write <= '0';
logic_func <= "00";
func <= "10";
branch_type <= "11";
pc_sel <= "00";
when "000100" =>
reg_write <= '0';
reg_dst <= '0';
reg_in_src <= '0';
alu_src <= '0';
add_sub <= '0';
data_write <= '0';
logic_func <= "00";
func <= "00";
branch_type <= "01";
pc_sel <= "00";
when others =>
reg_write <= '0';
reg_dst <= '0';
reg_in_src <= '0';
alu_src <= '0';
add_sub <= '0';
data_write <= '0';
logic_func <= "00";
func <= "10";
branch_type <= "10";
pc_sel <= "00";
end case;
end process;

end control_arch;

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